[S] Change in coreboot[master]: soc/amd/stoneyridge/acpi/sb_pci0_fch: report correct number of PCI buses - coreboot-gerrit

28 Apr 2023


      Attention is currently required from: Martin Roth, Felix Held.
Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74804 )
Change subject: soc/amd/stoneyridge/acpi/sb_pci0_fch: report correct number of PCI buses
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Patch Set 2: Code-Review+2
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I40121ab0e0438281192b6a0bec8dbecdc1749379
Gerrit-Change-Number: 74804
Gerrit-PatchSet: 2
Gerrit-Owner: Felix Held felix-coreboot@felixheld.de
Gerrit-Reviewer: Martin Roth martin.roth@amd.corp-partner.google.com
Gerrit-Reviewer: Matt DeVillier matt.devillier@amd.corp-partner.google.com
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Gerrit-Attention: Martin Roth martin.roth@amd.corp-partner.google.com
Gerrit-Attention: Felix Held felix-coreboot@felixheld.de
Gerrit-Comment-Date: Fri, 28 Apr 2023 18:55:34 +0000
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