Change in coreboot[master]: soc/intel/elkhartlake: Introduce Intel PSE

[Mario Scheithauer (Code Review)]

Attention is currently required from: Maulik V Vaghela, Paul Menzel, Angel Pons, Subrata Banik, Lean Sheng Tan, Patrick Rudolph.
Mario Scheithauer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55367 )

Change subject: soc/intel/elkhartlake: Introduce Intel PSE
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Patch Set 40:

(1 comment)

File src/soc/intel/elkhartlake/fsp_params.c:

https://review.coreboot.org/c/coreboot/+/55367/comment/70140f96_99077869 
PS39, Line 432: params->PchPseTimedGpioPinEnable[6] = 1;
Enabling PchPseTimedGpioPinEnable[6] will lead to an ASSERT when using FSP PV debug version. Why does this GPIO need to be enabled?