[S] Change in coreboot[master]: soc/amd/common/blk/pcie: Program LTR max latencies - coreboot-gerrit

9 Apr 2023


      Attention is currently required from: Jason Glenesk, Raul Rangel, Martin Roth, Fred Reitberger, Felix Held.
Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74288 )
Change subject: soc/amd/common/blk/pcie: Program LTR max latencies
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Patch Set 1:
(1 comment)
File src/soc/amd/common/block/pci/pcie_gpp.c:
https://review.coreboot.org/c/coreboot/+/74288/comment/e056f653_798a33fc 
PS1, Line 51: PCIE_LTR_MAX_LATENCY_1047US
...
How was this value determined?
value used by AGESA/FSP (and has been unchanged for 5 years per commit history), I'll update the commit msg with that info
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Icf188e69cf5676be870873c56d175423d16704b4
Gerrit-Change-Number: 74288
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