Change in coreboot[master]: soc/intel/alderlake: Create separate Kconfig for CLKSRC and CLKREQ

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50130 )

Change subject: soc/intel/alderlake: Create separate Kconfig for CLKSRC and CLKREQ
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soc/intel/alderlake: Create separate Kconfig for CLKSRC and CLKREQ

As per Hardware Architecture Specification (HAS) ADL-P has 7 CLKSRC
and 10 CLKREQ (7 SRCCLK is internal and 3 SRCCLK from external CLK chip).

ADL-M has 6 SRCCLK and CLKREQ (no external CLK chip).

Change-Id: I7d223c165f819669722cbc80245fa8ec20372352
Signed-off-by: Subrata Banik 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50130
Reviewed-by: EricR Lai 
Tested-by: build bot (Jenkins) 
---
M src/mainboard/intel/adlrvp/devicetree.cb
M src/soc/intel/alderlake/Kconfig
M src/soc/intel/alderlake/chip.h
3 files changed, 10 insertions(+), 8 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  EricR Lai: Looks good to me, approved

diff --git a/src/mainboard/intel/adlrvp/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb
index f2a8f377..0dd1456 100644
--- a/src/mainboard/intel/adlrvp/devicetree.cb
+++ b/src/mainboard/intel/adlrvp/devicetree.cb
@@ -84,9 +84,6 @@
    register "PchPcieRpEnable[2]" = "1"
    register "PchPcieRpEnable[3]" = "1"

-	# Mark LAN CLK pins as unused as GbE 0:0x1f.6 is disabled below
-	register "PcieClkSrcUsage[7]" = "PCIE_CLK_NOTUSED"
-
    register "SataSalpSupport" = "1"

register "SataPortsEnable" = "{
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
index 7289e02..806c91b 100644
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -139,10 +139,15 @@
    int
    default MAX_PCH_ROOT_PORTS

-config MAX_PCIE_CLOCKS
+config MAX_PCIE_CLOCK_SRC
    int
-	default 10 if SOC_INTEL_ALDERLAKE_PCH_M
-	default 12
+	default 6 if SOC_INTEL_ALDERLAKE_PCH_M
+	default 7
+
+config MAX_PCIE_CLOCK_REQ
+	int
+	default 6 if SOC_INTEL_ALDERLAKE_PCH_M
+	default 10

config SMM_TSEG_SIZE
    hex
diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h
index 70ceba7..0f932ce 100644
--- a/src/soc/intel/alderlake/chip.h
+++ b/src/soc/intel/alderlake/chip.h
@@ -131,10 +131,10 @@
    /* PCIe output clocks type to PCIe devices.
     * 0-23: PCH rootport, 0x70: LAN, 0x80: unspecified but in use,
     * 0xFF: not used */
-	uint8_t PcieClkSrcUsage[CONFIG_MAX_PCIE_CLOCKS];
+	uint8_t PcieClkSrcUsage[CONFIG_MAX_PCIE_CLOCK_SRC];
    /* PCIe ClkReq-to-ClkSrc mapping, number of clkreq signal assigned to
     * clksrc. */
-	uint8_t PcieClkSrcClkReq[CONFIG_MAX_PCIE_CLOCKS];
+	uint8_t PcieClkSrcClkReq[CONFIG_MAX_PCIE_CLOCK_REQ];

/* Probe CLKREQ# signal before enabling CLKREQ# based power management.*/
    uint8_t PcieRpClkReqDetect[CONFIG_MAX_PCH_ROOT_PORTS];