Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/82293?usp=email )
Change subject: soc/intel/xeon_sp: Move get_cxl_mode out of soc/util.h ......................................................................
soc/intel/xeon_sp: Move get_cxl_mode out of soc/util.h
get_cxl_mode() is the interface for CXL mode config check used by SoC codes. It could be implemented by mechanisms outside of the SoC codes, e.g. board codes or OCP VPD driver.
Move the interface declaration out of soc/util.h to a dedicated header, a.k.a., soc/config.h, so that the implementation codes do not need to include soc/util.h where there are lots of irrelevant definitions. Future SoC config check interfaces could be added to soc/config.h as well.
The default weak implementation is moved out of util.c to config.c as well.
TEST=Build and boot on intel/archercity CRB
Change-Id: Ia0302b0d3fd93c49e1d6f64e8159f59d50f33e20 Signed-off-by: Shuo Liu shuo.liu@intel.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/82293 Reviewed-by: Lean Sheng Tan sheng.tan@9elements.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/intel/archercity_crb/util.c M src/mainboard/inventec/transformers/romstage.c M src/mainboard/inventec/transformers/util.c M src/soc/intel/xeon_sp/Makefile.mk A src/soc/intel/xeon_sp/config.c M src/soc/intel/xeon_sp/include/soc/chip_common.h A src/soc/intel/xeon_sp/include/soc/config.h M src/soc/intel/xeon_sp/include/soc/util.h M src/soc/intel/xeon_sp/spr/romstage.c M src/soc/intel/xeon_sp/uncore.c M src/soc/intel/xeon_sp/util.c 11 files changed, 29 insertions(+), 17 deletions(-)
Approvals: Lean Sheng Tan: Looks good to me, approved build bot (Jenkins): Verified
diff --git a/src/mainboard/intel/archercity_crb/util.c b/src/mainboard/intel/archercity_crb/util.c index 0dac1e1..33afeca 100644 --- a/src/mainboard/intel/archercity_crb/util.c +++ b/src/mainboard/intel/archercity_crb/util.c @@ -1,8 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */
#include <drivers/ocp/include/vpd.h> -#include <soc/chip_common.h> -#include <soc/util.h> +#include <soc/config.h>
#if CONFIG(SOC_INTEL_HAS_CXL) && CONFIG(OCP_VPD) enum xeonsp_cxl_mode get_cxl_mode(void) diff --git a/src/mainboard/inventec/transformers/romstage.c b/src/mainboard/inventec/transformers/romstage.c index 1abcf70..25ff2d6 100644 --- a/src/mainboard/inventec/transformers/romstage.c +++ b/src/mainboard/inventec/transformers/romstage.c @@ -6,6 +6,7 @@ #include <drivers/ipmi/ipmi_if.h> #include <drivers/ipmi/ocp/ipmi_ocp.h> #include <drivers/ocp/ewl/ocp_ewl.h> +#include <soc/config.h> #include <soc/romstage.h> #include <defs_cxl.h> #include <defs_iio.h> diff --git a/src/mainboard/inventec/transformers/util.c b/src/mainboard/inventec/transformers/util.c index 5197b23..7b9237c 100644 --- a/src/mainboard/inventec/transformers/util.c +++ b/src/mainboard/inventec/transformers/util.c @@ -1,8 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */
#include <drivers/ocp/include/vpd.h> -#include <soc/chip_common.h> -#include <soc/util.h> +#include <soc/config.h>
#if CONFIG(SOC_INTEL_HAS_CXL) enum xeonsp_cxl_mode get_cxl_mode(void) diff --git a/src/soc/intel/xeon_sp/Makefile.mk b/src/soc/intel/xeon_sp/Makefile.mk index 3ebc6e0..35b998c 100644 --- a/src/soc/intel/xeon_sp/Makefile.mk +++ b/src/soc/intel/xeon_sp/Makefile.mk @@ -10,10 +10,12 @@
bootblock-y += bootblock.c spi.c lpc.c pch.c report_platform.c romstage-y += romstage.c reset.c util.c spi.c pmutil.c memmap.c ddr.c +romstage-y += config.c romstage-y += ../../../cpu/intel/car/romstage.c ramstage-y += uncore.c reset.c util.c lpc.c spi.c ramstage.c chip_common.c ramstage-y += memmap.c pch.c lockdown.c finalize.c ramstage-y += numa.c +ramstage-y += config.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PMC) += pmc.c pmutil.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += uncore_acpi.c acpi.c ramstage-$(CONFIG_SOC_INTEL_HAS_CXL) += uncore_acpi_cxl.c diff --git a/src/soc/intel/xeon_sp/config.c b/src/soc/intel/xeon_sp/config.c new file mode 100644 index 0000000..c2a908c --- /dev/null +++ b/src/soc/intel/xeon_sp/config.c @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/config.h> + +__weak enum xeonsp_cxl_mode get_cxl_mode(void) +{ + return XEONSP_CXL_DISABLED; +} diff --git a/src/soc/intel/xeon_sp/include/soc/chip_common.h b/src/soc/intel/xeon_sp/include/soc/chip_common.h index 5bdc87f..5fd5dc6 100644 --- a/src/soc/intel/xeon_sp/include/soc/chip_common.h +++ b/src/soc/intel/xeon_sp/include/soc/chip_common.h @@ -33,12 +33,6 @@ path->domain.domain = dp.domain_path; };
-enum xeonsp_cxl_mode { - XEONSP_CXL_DISABLED = 0, - XEONSP_CXL_SYS_MEM, - XEONSP_CXL_SP_MEM, -}; - /* * Every STACK can have multiple PCI domains with an unique domain type. * This is only of cosmetic nature and generates more readable ACPI code, diff --git a/src/soc/intel/xeon_sp/include/soc/config.h b/src/soc/intel/xeon_sp/include/soc/config.h new file mode 100644 index 0000000..6d5f3d5 --- /dev/null +++ b/src/soc/intel/xeon_sp/include/soc/config.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef _XEON_SP_SOC_CONFIG_H_ +#define _XEON_SP_SOC_CONFIG_H_ + +enum xeonsp_cxl_mode { + XEONSP_CXL_DISABLED = 0, + XEONSP_CXL_SYS_MEM, + XEONSP_CXL_SP_MEM, +}; + +enum xeonsp_cxl_mode get_cxl_mode(void); + +#endif diff --git a/src/soc/intel/xeon_sp/include/soc/util.h b/src/soc/intel/xeon_sp/include/soc/util.h index af74902..e694af3 100644 --- a/src/soc/intel/xeon_sp/include/soc/util.h +++ b/src/soc/intel/xeon_sp/include/soc/util.h @@ -31,6 +31,4 @@ union p2sb_bdf soc_get_hpet_bdf(void); union p2sb_bdf soc_get_ioapic_bdf(void);
-enum xeonsp_cxl_mode get_cxl_mode(void); - #endif diff --git a/src/soc/intel/xeon_sp/spr/romstage.c b/src/soc/intel/xeon_sp/spr/romstage.c index c339506..26bb308 100644 --- a/src/soc/intel/xeon_sp/spr/romstage.c +++ b/src/soc/intel/xeon_sp/spr/romstage.c @@ -20,6 +20,7 @@ #include <soc/soc_pch.h> #include <soc/intel/common/smbios.h> #include <string.h> +#include <soc/config.h> #include <soc/soc_util.h> #include <soc/util.h> #include <soc/ddr.h> diff --git a/src/soc/intel/xeon_sp/uncore.c b/src/soc/intel/xeon_sp/uncore.c index 4c22685..a6ac7c8 100644 --- a/src/soc/intel/xeon_sp/uncore.c +++ b/src/soc/intel/xeon_sp/uncore.c @@ -15,6 +15,7 @@ #include <fsp/util.h> #include <security/intel/txt/txt_platform.h> #include <security/intel/txt/txt.h> +#include <soc/config.h> #include <soc/numa.h> #include <soc/soc_util.h> #include <stdint.h> diff --git a/src/soc/intel/xeon_sp/util.c b/src/soc/intel/xeon_sp/util.c index 2fdf45e..4dbe7a4 100644 --- a/src/soc/intel/xeon_sp/util.c +++ b/src/soc/intel/xeon_sp/util.c @@ -265,8 +265,3 @@ set_bios_init_completion_for_package(sbsp_socket_id); } #endif - -__weak enum xeonsp_cxl_mode get_cxl_mode(void) -{ - return XEONSP_CXL_DISABLED; -}
-
Felix Held (Code Review)