Barnali Sarkar (barnali.sarkar@intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18418
-gerrit
commit 32bf161ddfbeaee58363a916a7224a6e5a0c03de Author: Barnali Sarkar barnali.sarkar@intel.com Date: Tue Feb 21 16:24:49 2017 +0530
soc/intel/common: Save Memory DIMM Information in SMBIOS Table
Save SMBIOS memory information from FSP MEM_INFO_DATA_HOB in CBMEM.
BUG=chrome-os-partner:61729 BRANCH=none TEST=Build and boot KBLRVP to verify the Type17 DIMM Info coming in SMBIOS Table from Kernel.
Change-Id: I0fd7c9887076d3fdd320fcbdcc873cb1965b950c Signed-off-by: Barnali Sarkar barnali.sarkar@intel.com --- src/soc/intel/common/Makefile.inc | 1 + src/soc/intel/common/smbios.c | 54 +++++++++++++++++++++++++++++++++++++++ src/soc/intel/common/smbios.h | 22 ++++++++++++++++ 3 files changed, 77 insertions(+)
diff --git a/src/soc/intel/common/Makefile.inc b/src/soc/intel/common/Makefile.inc index d6e1e75..25e51cd 100644 --- a/src/soc/intel/common/Makefile.inc +++ b/src/soc/intel/common/Makefile.inc @@ -13,6 +13,7 @@ romstage-$(CONFIG_SOC_INTEL_COMMON_LPSS_I2C) += lpss_i2c.c romstage-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c romstage-y += util.c romstage-$(CONFIG_MMA) += mma.c +romstage-y += smbios.c
postcar-y += util.c postcar-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c diff --git a/src/soc/intel/common/smbios.c b/src/soc/intel/common/smbios.c new file mode 100644 index 0000000..57426f2 --- /dev/null +++ b/src/soc/intel/common/smbios.c @@ -0,0 +1,54 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Intel Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <memory_info.h> +#include <string.h> +#include <smbios.h> +#include "smbios.h" +#include <console/console.h> + + +void dimm_info_fill(struct dimm_info *dimm, u32 dimm_capacity, u8 ddr_type, + u32 frequency, u8 channel_id, u8 dimm_id, u8 *module_part_num, u16 data_width) +{ + dimm->dimm_size = dimm_capacity; + dimm->ddr_type = ddr_type; + dimm->ddr_frequency = frequency; + dimm->channel_num = channel_id; + dimm->dimm_num = dimm_id; + strncpy((char *)dimm->module_part_number, + (char *)module_part_num, + sizeof(dimm->module_part_number)); + switch (data_width) { + case 8: + dimm->bus_width = MEMORY_BUS_WIDTH_8; + break; + case 16: + dimm->bus_width = MEMORY_BUS_WIDTH_16; + break; + case 32: + dimm->bus_width = MEMORY_BUS_WIDTH_32; + break; + case 64: + dimm->bus_width = MEMORY_BUS_WIDTH_64; + break; + case 128: + dimm->bus_width = MEMORY_BUS_WIDTH_128; + break; + default: + printk(BIOS_ERR, "Incorrect DIMM Data Width"); + } +} diff --git a/src/soc/intel/common/smbios.h b/src/soc/intel/common/smbios.h new file mode 100644 index 0000000..66526bd --- /dev/null +++ b/src/soc/intel/common/smbios.h @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Intel Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _COMMON_SMBIOS_H_ +#define _COMMON_SMBIOS_H_ + +void dimm_info_fill(struct dimm_info *dimm, u32 dimm_capacity, u8 ddr_type, + u32 frequency, u8 channel_id, u8 dimm_id, u8 *module_part_num, u16 data_width); + +#endif /* _COMMON_SMBIOS_H_ */