[XS] Change in coreboot[main]: soc/intel/alderlake: Correctly set CNVi Reset and Clkreq pins

[Sean Rhodes (Code Review)]

Attention is currently required from: Dinesh Gehlot, Kapil Porwal, Martin L Roth, Nick Vaccaro, Sean Rhodes, Subrata Banik, [e-mail].

Hello Dinesh Gehlot, Kapil Porwal, Martin L Roth, Nick Vaccaro, Subrata Banik, build bot (Jenkins), [e-mail],

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/81080?usp=email

to look at the new patch set (#5).

The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)

Change subject: soc/intel/alderlake: Correctly set CNVi Reset and Clkreq pins
......................................................................

soc/intel/alderlake: Correctly set CNVi Reset and Clkreq pins

FSP will default to using GPP_A8 for the reset pin, and GPP_A9 for
the Clkreq. These two pins are reserved for eSPI.

Set these to GPP_F4 and GPP_F5 respectively, as coreboot only supports
eSPI.

Signed-off-by: Sean Rhodes 
Change-Id: Ib534d3cfe888c1c538267caaf324c8ae743da496
---
M src/soc/intel/alderlake/fsp_params.c
1 file changed, 8 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/81080/5