Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33763
Change subject: _WIP_ soc/amd/picasso: Update i2c support ......................................................................
_WIP_ soc/amd/picasso: Update i2c support
* todo: pad config
Change the stoneyridge definitions into picasso. The named 0 and 1 buses are controlled by the PSP and not directly accessible by host firmware. I2C4 operates only in slave mode so is not added to to the bus clear-after-reset sequence.
The I2C controller is fundamentally the same as on Stoney Ridge so the ability to clear a potentially jammed bus is still required. I2C4 operates only in slave mode so is not added to to the bus clear-after-reset sequence.
Signed-off-by: Marshall Dawson marshalldawson3rd@gmail.com Change-Id: Ibbc5504ebc36654e28c79fe3ae17cc0d9255118f --- M src/soc/amd/picasso/acpi/globalnvs.asl M src/soc/amd/picasso/acpi/sb_pci0_fch.asl M src/soc/amd/picasso/i2c.c M src/soc/amd/picasso/include/soc/i2c.h M src/soc/amd/picasso/include/soc/iomap.h M src/soc/amd/picasso/include/soc/southbridge.h M src/soc/amd/picasso/southbridge.c 7 files changed, 43 insertions(+), 74 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/33763/1
diff --git a/src/soc/amd/picasso/acpi/globalnvs.asl b/src/soc/amd/picasso/acpi/globalnvs.asl index cdb32cc..355fbeb 100644 --- a/src/soc/amd/picasso/acpi/globalnvs.asl +++ b/src/soc/amd/picasso/acpi/globalnvs.asl @@ -48,12 +48,11 @@ TPSV, 8, // 0x2F - Passive Threshold TMAX, 8, // 0x30 - CPU Tj_max Offset (0x34), // 0x34 - AOAC Device Enables - , 5, - IC0E, 1, // I2C0, 5 - IC1E, 1, // I2C1, 6 + , 7, IC2E, 1, // I2C2, 7 IC3E, 1, // I2C3, 8 - , 2, + IC4E, 1, // I2C4, 9 + , 1, UT0E, 1, // UART0, 11 UT1E, 1, // UART1, 12 , 2, diff --git a/src/soc/amd/picasso/acpi/sb_pci0_fch.asl b/src/soc/amd/picasso/acpi/sb_pci0_fch.asl index 8cdb4d2..1d8768b 100644 --- a/src/soc/amd/picasso/acpi/sb_pci0_fch.asl +++ b/src/soc/amd/picasso/acpi/sb_pci0_fch.asl @@ -530,16 +530,6 @@ FDDC(12, 3) } } - if(LEqual(\IC0E, zero)) { - if(LNotEqual(I0TD, 0x03)) { - FDDC(5, 3) - } - } - if(LEqual(\IC1E, zero)) { - if(LNotEqual(I1TD, 0x03)) { - FDDC(6, 3) - } - } if(LEqual(\IC2E, zero)) { if(LNotEqual(I2TD, 0x03)) { FDDC(7, 3) diff --git a/src/soc/amd/picasso/i2c.c b/src/soc/amd/picasso/i2c.c index 9fe1588..27d7885 100644 --- a/src/soc/amd/picasso/i2c.c +++ b/src/soc/amd/picasso/i2c.c @@ -25,25 +25,21 @@ #include <soc/i2c.h> #include "chip.h"
-#define I2C_BUS_ADDRESS(x) (I2C_BASE_ADDRESS + I2C_DEVICE_SIZE * (x)) -#define I2CA_BASE_ADDRESS (I2C_BUS_ADDRESS(0)) -#define I2CB_BASE_ADDRESS (I2C_BUS_ADDRESS(1)) -#define I2CC_BASE_ADDRESS (I2C_BUS_ADDRESS(2)) -#define I2CD_BASE_ADDRESS (I2C_BUS_ADDRESS(3)) - /* Global to provide access to chip.c */ const char *i2c_acpi_name(const struct device *dev);
static const uintptr_t i2c_bus_address[] = { - I2CA_BASE_ADDRESS, - I2CB_BASE_ADDRESS, - I2CC_BASE_ADDRESS, - I2CD_BASE_ADDRESS, + APU_I2C2_BASE, + APU_I2C3_BASE, + APU_I2C4_BASE, /* slave device only */ };
uintptr_t dw_i2c_base_address(unsigned int bus) { - return bus < I2C_DEVICE_COUNT ? i2c_bus_address[bus] : 0; + if (bus < APU_I2C_MIN_BUS || bus > APU_I2C_MAX_BUS) + return 0; + + return i2c_bus_address[bus - APU_I2C_MIN_BUS]; }
static const struct soc_amd_picasso_config *get_soc_config(void) @@ -63,7 +59,7 @@ { const struct soc_amd_picasso_config *config;
- if (bus >= ARRAY_SIZE(i2c_bus_address)) + if (bus < APU_I2C_MIN_BUS || bus > APU_I2C_MAX_BUS) return NULL;
config = get_soc_config(); @@ -76,14 +72,12 @@ const char *i2c_acpi_name(const struct device *dev) { switch (dev->path.mmio.addr) { - case I2CA_BASE_ADDRESS: - return "I2CA"; - case I2CB_BASE_ADDRESS: - return "I2CB"; - case I2CC_BASE_ADDRESS: + case APU_I2C2_BASE: return "I2CC"; - case I2CD_BASE_ADDRESS: + case APU_I2C3_BASE: return "I2CD"; + case APU_I2C4_BASE: + return "I2CE"; default: return NULL; } @@ -92,18 +86,17 @@ int dw_i2c_soc_dev_to_bus(struct device *dev) { switch (dev->path.mmio.addr) { - case I2CA_BASE_ADDRESS: - return 0; - case I2CB_BASE_ADDRESS: - return 1; - case I2CC_BASE_ADDRESS: + case APU_I2C2_BASE: return 2; - case I2CD_BASE_ADDRESS: + case APU_I2C3_BASE: return 3; + case APU_I2C4_BASE: + return 4; } return -1; }
+/* TODO: MISC::I2C[n]_PadCtrl may require programming */ static void dw_i2c_soc_init(bool is_early_init) { size_t i; @@ -152,10 +145,9 @@ * conversion of all SCL pins to input with no pull. */ static const struct soc_amd_gpio i2c_2_gpi[] = { - PAD_GPI(I2C0_SCL_PIN, PULL_NONE), - PAD_GPI(I2C1_SCL_PIN, PULL_NONE), PAD_GPI(I2C2_SCL_PIN, PULL_NONE), PAD_GPI(I2C3_SCL_PIN, PULL_NONE), + /* I2C4 is a slave device only */ }; #define saved_pins_count ARRAY_SIZE(i2c_2_gpi)
@@ -210,10 +202,6 @@ * needed after the writes to force the posted write to complete. */ for (j = 0; j < 9; j++) { - if (control & GPIO_I2C0_SCL) - write32((uint32_t *)GPIO_I2C0_ADDRESS, GPIO_SCL_LOW); - if (control & GPIO_I2C1_SCL) - write32((uint32_t *)GPIO_I2C1_ADDRESS, GPIO_SCL_LOW); if (control & GPIO_I2C2_SCL) write32((uint32_t *)GPIO_I2C2_ADDRESS, GPIO_SCL_LOW); if (control & GPIO_I2C3_SCL) @@ -222,10 +210,6 @@ read32((uint32_t *)GPIO_I2C3_ADDRESS); /* Flush posted write */ udelay(4); /* 4usec gets 85KHz for 1 pin, 70KHz for 4 pins */
- if (control & GPIO_I2C0_SCL) - write32((uint32_t *)GPIO_I2C0_ADDRESS, GPIO_SCL_HIGH); - if (control & GPIO_I2C1_SCL) - write32((uint32_t *)GPIO_I2C1_ADDRESS, GPIO_SCL_HIGH); if (control & GPIO_I2C2_SCL) write32((uint32_t *)GPIO_I2C2_ADDRESS, GPIO_SCL_HIGH); if (control & GPIO_I2C3_SCL) diff --git a/src/soc/amd/picasso/include/soc/i2c.h b/src/soc/amd/picasso/include/soc/i2c.h index fb9b113..d129fc1 100644 --- a/src/soc/amd/picasso/include/soc/i2c.h +++ b/src/soc/amd/picasso/include/soc/i2c.h @@ -23,24 +23,18 @@ uint8_t mux_value; };
-#define GPIO_I2C0_SCL BIT(0) -#define GPIO_I2C1_SCL BIT(1) -#define GPIO_I2C2_SCL BIT(2) -#define GPIO_I2C3_SCL BIT(3) -#define GPIO_I2C_MASK (BIT(0) | BIT(1) | BIT(2) | BIT(3)) +#define GPIO_I2C2_SCL BIT(2) +#define GPIO_I2C3_SCL BIT(3) +#define GPIO_I2C_MASK (BIT(2) | BIT(3))
-#define I2C0_SCL_PIN GPIO_145 -#define I2C1_SCL_PIN GPIO_147 #define I2C2_SCL_PIN GPIO_113 #define I2C3_SCL_PIN GPIO_19
-#define GPIO_I2C0_ADDRESS GPIO_BANK2_CONTROL(I2C0_SCL_PIN) -#define GPIO_I2C1_ADDRESS GPIO_BANK2_CONTROL(I2C1_SCL_PIN) #define GPIO_I2C2_ADDRESS GPIO_BANK1_CONTROL(I2C2_SCL_PIN) #define GPIO_I2C3_ADDRESS GPIO_BANK0_CONTROL(I2C3_SCL_PIN) +#define GPIO_SCL_HIGH 0 +#define GPIO_SCL_LOW GPIO_OUTPUT_ENABLE
-#define I2C0_SCL_PIN_IOMUX_GPIOxx GPIO_145_IOMUX_GPIOxx -#define I2C1_SCL_PIN_IOMUX_GPIOxx GPIO_147_IOMUX_GPIOxx #define I2C2_SCL_PIN_IOMUX_GPIOxx GPIO_113_IOMUX_GPIOxx #define I2C3_SCL_PIN_IOMUX_GPIOxx GPIO_19_IOMUX_GPIOxx
diff --git a/src/soc/amd/picasso/include/soc/iomap.h b/src/soc/amd/picasso/include/soc/iomap.h index 1d89fd7..b9d1ab5 100644 --- a/src/soc/amd/picasso/include/soc/iomap.h +++ b/src/soc/amd/picasso/include/soc/iomap.h @@ -43,9 +43,16 @@ #define ALINK_AHB_ADDRESS 0xfedc0000
/* I2C fixed address */ -#define I2C_BASE_ADDRESS 0xfedc2000 +#define APU_I2C2_BASE 0xfedc4000 +#define APU_I2C3_BASE 0xfedc5000 +#define APU_I2C4_BASE 0xfedc6000 +#define APU_I2C_MIN_BUS 2 +#define APU_I2C_MAX_BUS 4 +#define APU_I2C_BLOCK_SIZE 0x1000 +#define I2C_BASE_ADDRESS APU_I2C2_BASE #define I2C_DEVICE_SIZE 0x00001000 -#define I2C_DEVICE_COUNT 4 +#define I2C_DEVICE_COUNT 3 +
#if CONFIG(HPET_ADDRESS_OVERRIDE) #error HPET address override is not allowed and must be fixed at 0xfed00000 diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h index 6733946..04e9a25 100644 --- a/src/soc/amd/picasso/include/soc/southbridge.h +++ b/src/soc/amd/picasso/include/soc/southbridge.h @@ -180,10 +180,9 @@
/* FCH AOAC Registers 0xfed81e00 */ #define FCH_AOAC_D3_CONTROL_CLK_GEN 0x40 -#define FCH_AOAC_D3_CONTROL_I2C0 0x4a -#define FCH_AOAC_D3_CONTROL_I2C1 0x4c #define FCH_AOAC_D3_CONTROL_I2C2 0x4e #define FCH_AOAC_D3_CONTROL_I2C3 0x50 +#define FCH_AOAC_D3_CONTROL_I2C4 0x52 #define FCH_AOAC_D3_CONTROL_UART0 0x56 #define FCH_AOAC_D3_CONTROL_UART1 0x58 #define FCH_AOAC_D3_CONTROL_AMBA 0x62 @@ -199,10 +198,9 @@ #define FCH_AOAC_IS_SW_CONTROL BIT(7)
#define FCH_AOAC_D3_STATE_CLK_GEN 0x41 -#define FCH_AOAC_D3_STATE_I2C0 0x4b -#define FCH_AOAC_D3_STATE_I2C1 0x4d #define FCH_AOAC_D3_STATE_I2C2 0x4f #define FCH_AOAC_D3_STATE_I2C3 0x51 +#define FCH_AOAC_D3_STATE_I2C4 0x53 #define FCH_AOAC_D3_STATE_UART0 0x57 #define FCH_AOAC_D3_STATE_UART1 0x59 #define FCH_AOAC_D3_STATE_AMBA 0x63 @@ -290,12 +288,11 @@ };
typedef struct aoac_devs { - unsigned int :5; - unsigned int ic0e:1; /* 5: I2C0 */ - unsigned int ic1e:1; /* 6: I2C1 */ + unsigned int :7; unsigned int ic2e:1; /* 7: I2C2 */ unsigned int ic3e:1; /* 8: I2C3 */ - unsigned int :2; + unsigned int ic4e:1; /* 9: I2C4 */ + unsigned int :1; unsigned int ut0e:1; /* 11: UART0 */ unsigned int ut1e:1; /* 12: UART1 */ unsigned int :2; diff --git a/src/soc/amd/picasso/southbridge.c b/src/soc/amd/picasso/southbridge.c index d0e12a9..f487d08 100644 --- a/src/soc/amd/picasso/southbridge.c +++ b/src/soc/amd/picasso/southbridge.c @@ -46,10 +46,9 @@ { (FCH_AOAC_D3_CONTROL_UART0 + CONFIG_UART_FOR_CONSOLE * 2), (FCH_AOAC_D3_STATE_UART0 + CONFIG_UART_FOR_CONSOLE * 2) }, { FCH_AOAC_D3_CONTROL_AMBA, FCH_AOAC_D3_STATE_AMBA }, - { FCH_AOAC_D3_CONTROL_I2C0, FCH_AOAC_D3_STATE_I2C0 }, - { FCH_AOAC_D3_CONTROL_I2C1, FCH_AOAC_D3_STATE_I2C1 }, { FCH_AOAC_D3_CONTROL_I2C2, FCH_AOAC_D3_STATE_I2C2 }, - { FCH_AOAC_D3_CONTROL_I2C3, FCH_AOAC_D3_STATE_I2C3 } + { FCH_AOAC_D3_CONTROL_I2C3, FCH_AOAC_D3_STATE_I2C3 }, + { FCH_AOAC_D3_CONTROL_I2C4, FCH_AOAC_D3_STATE_I2C4 } };
/* @@ -528,10 +527,9 @@ if (gnvs == NULL) return;
- gnvs->aoac.ic0e = is_aoac_device_enabled(FCH_AOAC_D3_STATE_I2C0); - gnvs->aoac.ic1e = is_aoac_device_enabled(FCH_AOAC_D3_STATE_I2C1); gnvs->aoac.ic2e = is_aoac_device_enabled(FCH_AOAC_D3_STATE_I2C2); gnvs->aoac.ic3e = is_aoac_device_enabled(FCH_AOAC_D3_STATE_I2C3); + gnvs->aoac.ic4e = is_aoac_device_enabled(FCH_AOAC_D3_STATE_I2C4); gnvs->aoac.ut0e = is_aoac_device_enabled(FCH_AOAC_D3_STATE_UART0); gnvs->aoac.ut1e = is_aoac_device_enabled(FCH_AOAC_D3_STATE_UART1); /* Rely on these being in sync with devicetree */
Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33763 )
Change subject: soc/amd/picasso: Update i2c support ......................................................................
Patch Set 9: Code-Review+2
(1 comment)
https://review.coreboot.org/c/coreboot/+/33763/9//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/33763/9//COMMIT_MSG@16 PS9, Line 16: I2C4 operates only in slave mode so is not added to to the bus : clear-after-reset sequence. : This same text is in the previous paragraph
Hello build bot (Jenkins), Martin Roth, Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/33763
to look at the new patch set (#10).
Change subject: soc/amd/picasso: Update i2c support ......................................................................
soc/amd/picasso: Update i2c support
Change the stoneyridge definitions into picasso. The named 0 and 1 buses are controlled by the PSP and not directly accessible by host firmware. I2C4 operates only in slave mode so is not added to to the bus clear-after-reset sequence.
The I2C controller is fundamentally the same as on Stoney Ridge so the ability to clear a potentially jammed bus is still required.
Program Picasso's new pad control registers in the MISC AcpiMmio space according to the recommended settings.
Signed-off-by: Marshall Dawson marshalldawson3rd@gmail.com Change-Id: Ibbc5504ebc36654e28c79fe3ae17cc0d9255118f --- M src/soc/amd/picasso/acpi/globalnvs.asl M src/soc/amd/picasso/acpi/sb_pci0_fch.asl M src/soc/amd/picasso/i2c.c M src/soc/amd/picasso/include/soc/i2c.h M src/soc/amd/picasso/include/soc/iomap.h M src/soc/amd/picasso/include/soc/southbridge.h M src/soc/amd/picasso/southbridge.c 7 files changed, 96 insertions(+), 75 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/33763/10
Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33763 )
Change subject: soc/amd/picasso: Update i2c support ......................................................................
Patch Set 10:
(1 comment)
https://review.coreboot.org/c/coreboot/+/33763/9//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/33763/9//COMMIT_MSG@16 PS9, Line 16: I2C4 operates only in slave mode so is not added to to the bus : clear-after-reset sequence. :
This same text is in the previous paragraph
Done
Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/33763 )
Change subject: soc/amd/picasso: Update i2c support ......................................................................
soc/amd/picasso: Update i2c support
Change the stoneyridge definitions into picasso. The named 0 and 1 buses are controlled by the PSP and not directly accessible by host firmware. I2C4 operates only in slave mode so is not added to to the bus clear-after-reset sequence.
The I2C controller is fundamentally the same as on Stoney Ridge so the ability to clear a potentially jammed bus is still required.
Program Picasso's new pad control registers in the MISC AcpiMmio space according to the recommended settings.
Signed-off-by: Marshall Dawson marshalldawson3rd@gmail.com Change-Id: Ibbc5504ebc36654e28c79fe3ae17cc0d9255118f Reviewed-on: https://review.coreboot.org/c/coreboot/+/33763 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Martin Roth martinroth@google.com --- M src/soc/amd/picasso/acpi/globalnvs.asl M src/soc/amd/picasso/acpi/sb_pci0_fch.asl M src/soc/amd/picasso/i2c.c M src/soc/amd/picasso/include/soc/i2c.h M src/soc/amd/picasso/include/soc/iomap.h M src/soc/amd/picasso/include/soc/southbridge.h M src/soc/amd/picasso/southbridge.c 7 files changed, 96 insertions(+), 75 deletions(-)
Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved
diff --git a/src/soc/amd/picasso/acpi/globalnvs.asl b/src/soc/amd/picasso/acpi/globalnvs.asl index cc264e6..04e41a1 100644 --- a/src/soc/amd/picasso/acpi/globalnvs.asl +++ b/src/soc/amd/picasso/acpi/globalnvs.asl @@ -48,12 +48,11 @@ TPSV, 8, // 0x2F - Passive Threshold TMAX, 8, // 0x30 - CPU Tj_max Offset (0x34), // 0x34 - AOAC Device Enables - , 5, - IC0E, 1, // I2C0, 5 - IC1E, 1, // I2C1, 6 + , 7, IC2E, 1, // I2C2, 7 IC3E, 1, // I2C3, 8 - , 2, + IC4E, 1, // I2C4, 9 + , 1, UT0E, 1, // UART0, 11 UT1E, 1, // UART1, 12 , 2, diff --git a/src/soc/amd/picasso/acpi/sb_pci0_fch.asl b/src/soc/amd/picasso/acpi/sb_pci0_fch.asl index 206fdfd..b9eeadb 100644 --- a/src/soc/amd/picasso/acpi/sb_pci0_fch.asl +++ b/src/soc/amd/picasso/acpi/sb_pci0_fch.asl @@ -484,16 +484,6 @@ FDDC(12, 3) } } - if(LEqual(\IC0E, zero)) { - if(LNotEqual(I0TD, 0x03)) { - FDDC(5, 3) - } - } - if(LEqual(\IC1E, zero)) { - if(LNotEqual(I1TD, 0x03)) { - FDDC(6, 3) - } - } if(LEqual(\IC2E, zero)) { if(LNotEqual(I2TD, 0x03)) { FDDC(7, 3) diff --git a/src/soc/amd/picasso/i2c.c b/src/soc/amd/picasso/i2c.c index 9fe1588..8786643 100644 --- a/src/soc/amd/picasso/i2c.c +++ b/src/soc/amd/picasso/i2c.c @@ -25,25 +25,21 @@ #include <soc/i2c.h> #include "chip.h"
-#define I2C_BUS_ADDRESS(x) (I2C_BASE_ADDRESS + I2C_DEVICE_SIZE * (x)) -#define I2CA_BASE_ADDRESS (I2C_BUS_ADDRESS(0)) -#define I2CB_BASE_ADDRESS (I2C_BUS_ADDRESS(1)) -#define I2CC_BASE_ADDRESS (I2C_BUS_ADDRESS(2)) -#define I2CD_BASE_ADDRESS (I2C_BUS_ADDRESS(3)) - /* Global to provide access to chip.c */ const char *i2c_acpi_name(const struct device *dev);
static const uintptr_t i2c_bus_address[] = { - I2CA_BASE_ADDRESS, - I2CB_BASE_ADDRESS, - I2CC_BASE_ADDRESS, - I2CD_BASE_ADDRESS, + APU_I2C2_BASE, + APU_I2C3_BASE, + APU_I2C4_BASE, /* slave device only */ };
uintptr_t dw_i2c_base_address(unsigned int bus) { - return bus < I2C_DEVICE_COUNT ? i2c_bus_address[bus] : 0; + if (bus < APU_I2C_MIN_BUS || bus > APU_I2C_MAX_BUS) + return 0; + + return i2c_bus_address[bus - APU_I2C_MIN_BUS]; }
static const struct soc_amd_picasso_config *get_soc_config(void) @@ -63,7 +59,7 @@ { const struct soc_amd_picasso_config *config;
- if (bus >= ARRAY_SIZE(i2c_bus_address)) + if (bus < APU_I2C_MIN_BUS || bus > APU_I2C_MAX_BUS) return NULL;
config = get_soc_config(); @@ -76,14 +72,12 @@ const char *i2c_acpi_name(const struct device *dev) { switch (dev->path.mmio.addr) { - case I2CA_BASE_ADDRESS: - return "I2CA"; - case I2CB_BASE_ADDRESS: - return "I2CB"; - case I2CC_BASE_ADDRESS: + case APU_I2C2_BASE: return "I2CC"; - case I2CD_BASE_ADDRESS: + case APU_I2C3_BASE: return "I2CD"; + case APU_I2C4_BASE: + return "I2CE"; default: return NULL; } @@ -92,22 +86,24 @@ int dw_i2c_soc_dev_to_bus(struct device *dev) { switch (dev->path.mmio.addr) { - case I2CA_BASE_ADDRESS: - return 0; - case I2CB_BASE_ADDRESS: - return 1; - case I2CC_BASE_ADDRESS: + case APU_I2C2_BASE: return 2; - case I2CD_BASE_ADDRESS: + case APU_I2C3_BASE: return 3; + case APU_I2C4_BASE: + return 4; } return -1; }
+__weak void mainboard_i2c_override(int bus, uint32_t *pad_settings) { } + static void dw_i2c_soc_init(bool is_early_init) { size_t i; const struct soc_amd_picasso_config *config; + uint32_t pad_ctrl; + int misc_reg;
config = get_soc_config();
@@ -120,8 +116,28 @@ if (cfg->early_init != is_early_init) continue;
- if (dw_i2c_init(i, cfg)) + if (dw_i2c_init(i, cfg)) { printk(BIOS_ERR, "Failed to init i2c bus %zd\n", i); + continue; + } + + misc_reg = MISC_I2C0_PAD_CTRL + sizeof(uint32_t) * i; + pad_ctrl = misc_read32(misc_reg); + + pad_ctrl &= ~I2C_PAD_CTRL_NG_MASK; + pad_ctrl |= I2C_PAD_CTRL_NG_NORMAL; + + pad_ctrl &= ~I2C_PAD_CTRL_RX_SEL_MASK; + pad_ctrl |= I2C_PAD_CTRL_RX_SEL_3_3V; + + pad_ctrl &= ~I2C_PAD_CTRL_FALLSLEW_MASK; + pad_ctrl |= cfg->speed == I2C_SPEED_STANDARD + ? I2C_PAD_CTRL_FALLSLEW_STD + : I2C_PAD_CTRL_FALLSLEW_LOW; + pad_ctrl |= I2C_PAD_CTRL_FALLSLEW_EN; + + mainboard_i2c_override(i, &pad_ctrl); + misc_write32(misc_reg, pad_ctrl); } }
@@ -152,10 +168,9 @@ * conversion of all SCL pins to input with no pull. */ static const struct soc_amd_gpio i2c_2_gpi[] = { - PAD_GPI(I2C0_SCL_PIN, PULL_NONE), - PAD_GPI(I2C1_SCL_PIN, PULL_NONE), PAD_GPI(I2C2_SCL_PIN, PULL_NONE), PAD_GPI(I2C3_SCL_PIN, PULL_NONE), + /* I2C4 is a slave device only */ }; #define saved_pins_count ARRAY_SIZE(i2c_2_gpi)
@@ -210,10 +225,6 @@ * needed after the writes to force the posted write to complete. */ for (j = 0; j < 9; j++) { - if (control & GPIO_I2C0_SCL) - write32((uint32_t *)GPIO_I2C0_ADDRESS, GPIO_SCL_LOW); - if (control & GPIO_I2C1_SCL) - write32((uint32_t *)GPIO_I2C1_ADDRESS, GPIO_SCL_LOW); if (control & GPIO_I2C2_SCL) write32((uint32_t *)GPIO_I2C2_ADDRESS, GPIO_SCL_LOW); if (control & GPIO_I2C3_SCL) @@ -222,10 +233,6 @@ read32((uint32_t *)GPIO_I2C3_ADDRESS); /* Flush posted write */ udelay(4); /* 4usec gets 85KHz for 1 pin, 70KHz for 4 pins */
- if (control & GPIO_I2C0_SCL) - write32((uint32_t *)GPIO_I2C0_ADDRESS, GPIO_SCL_HIGH); - if (control & GPIO_I2C1_SCL) - write32((uint32_t *)GPIO_I2C1_ADDRESS, GPIO_SCL_HIGH); if (control & GPIO_I2C2_SCL) write32((uint32_t *)GPIO_I2C2_ADDRESS, GPIO_SCL_HIGH); if (control & GPIO_I2C3_SCL) diff --git a/src/soc/amd/picasso/include/soc/i2c.h b/src/soc/amd/picasso/include/soc/i2c.h index fb9b113..d129fc1 100644 --- a/src/soc/amd/picasso/include/soc/i2c.h +++ b/src/soc/amd/picasso/include/soc/i2c.h @@ -23,24 +23,18 @@ uint8_t mux_value; };
-#define GPIO_I2C0_SCL BIT(0) -#define GPIO_I2C1_SCL BIT(1) -#define GPIO_I2C2_SCL BIT(2) -#define GPIO_I2C3_SCL BIT(3) -#define GPIO_I2C_MASK (BIT(0) | BIT(1) | BIT(2) | BIT(3)) +#define GPIO_I2C2_SCL BIT(2) +#define GPIO_I2C3_SCL BIT(3) +#define GPIO_I2C_MASK (BIT(2) | BIT(3))
-#define I2C0_SCL_PIN GPIO_145 -#define I2C1_SCL_PIN GPIO_147 #define I2C2_SCL_PIN GPIO_113 #define I2C3_SCL_PIN GPIO_19
-#define GPIO_I2C0_ADDRESS GPIO_BANK2_CONTROL(I2C0_SCL_PIN) -#define GPIO_I2C1_ADDRESS GPIO_BANK2_CONTROL(I2C1_SCL_PIN) #define GPIO_I2C2_ADDRESS GPIO_BANK1_CONTROL(I2C2_SCL_PIN) #define GPIO_I2C3_ADDRESS GPIO_BANK0_CONTROL(I2C3_SCL_PIN) +#define GPIO_SCL_HIGH 0 +#define GPIO_SCL_LOW GPIO_OUTPUT_ENABLE
-#define I2C0_SCL_PIN_IOMUX_GPIOxx GPIO_145_IOMUX_GPIOxx -#define I2C1_SCL_PIN_IOMUX_GPIOxx GPIO_147_IOMUX_GPIOxx #define I2C2_SCL_PIN_IOMUX_GPIOxx GPIO_113_IOMUX_GPIOxx #define I2C3_SCL_PIN_IOMUX_GPIOxx GPIO_19_IOMUX_GPIOxx
diff --git a/src/soc/amd/picasso/include/soc/iomap.h b/src/soc/amd/picasso/include/soc/iomap.h index 4e11cbd..ad0e7c4 100644 --- a/src/soc/amd/picasso/include/soc/iomap.h +++ b/src/soc/amd/picasso/include/soc/iomap.h @@ -44,9 +44,16 @@ #define ALINK_AHB_ADDRESS 0xfedc0000
/* I2C fixed address */ -#define I2C_BASE_ADDRESS 0xfedc2000 +#define APU_I2C2_BASE 0xfedc4000 +#define APU_I2C3_BASE 0xfedc5000 +#define APU_I2C4_BASE 0xfedc6000 +#define APU_I2C_MIN_BUS 2 +#define APU_I2C_MAX_BUS 4 +#define APU_I2C_BLOCK_SIZE 0x1000 +#define I2C_BASE_ADDRESS APU_I2C2_BASE #define I2C_DEVICE_SIZE 0x00001000 -#define I2C_DEVICE_COUNT 4 +#define I2C_DEVICE_COUNT 3 +
#if CONFIG(HPET_ADDRESS_OVERRIDE) #error HPET address override is not allowed and must be fixed at 0xfed00000 diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h index 8c96aa7..803c638 100644 --- a/src/soc/amd/picasso/include/soc/southbridge.h +++ b/src/soc/amd/picasso/include/soc/southbridge.h @@ -178,13 +178,38 @@ #define BP_X48M0_OUTPUT_EN BIT(2) /* 1=En, unlike Hudson, Kern */ #define OSCOUT1_CLK_OUTPUT_ENB BIT(2) /* 0 = Enabled, 1 = Disabled */ #define OSCOUT2_CLK_OUTPUT_ENB BIT(7) /* 0 = Enabled, 1 = Disabled */ +#define MISC_I2C0_PAD_CTRL 0xd8 +#define MISC_I2C1_PAD_CTRL 0xdc +#define MISC_I2C2_PAD_CTRL 0xe0 +#define MISC_I2C3_PAD_CTRL 0xe4 +#define I2C_PAD_CTRL_NG_MASK (BIT(0) + BIT(1) + BIT(2) + BIT(3)) +#define I2C_PAD_CTRL_NG_NORMAL 0xc +#define I2C_PAD_CTRL_RX_SEL_MASK (BIT(4) + BIT(5)) +#define I2C_PAD_CTRL_RX_SHIFT 4 +#define I2C_PAD_CTRL_RX_SEL_OFF (0 << I2C_PAD_CTRL_RX_SHIFT) +#define I2C_PAD_CTRL_RX_SEL_3_3V (1 << I2C_PAD_CTRL_RX_SHIFT) +#define I2C_PAD_CTRL_RX_SEL_1_8V (3 << I2C_PAD_CTRL_RX_SHIFT) +#define I2C_PAD_CTRL_PULLDOWN_EN BIT(6) +#define I2C_PAD_CTRL_FALLSLEW_MASK (BIT(7) + BIT(8)) +#define I2C_PAD_CTRL_FALLSLEW_SHIFT 7 +#define I2C_PAD_CTRL_FALLSLEW_STD (0 << I2C_PAD_CTRL_FALLSLEW_SHIFT) +#define I2C_PAD_CTRL_FALLSLEW_LOW (1 << I2C_PAD_CTRL_FALLSLEW_SHIFT) +#define I2C_PAD_CTRL_FALLSLEW_EN BIT(9) +#define I2C_PAD_CTRL_SPIKE_RC_EN BIT(10) +#define I2C_PAD_CTRL_SPIKE_RC_SEL BIT(11) /* 0 = 50ns, 1 = 20ns */ +#define I2C_PAD_CTRL_CAP_DOWN BIT(12) +#define I2C_PAD_CTRL_CAP_UP BIT(13) +#define I2C_PAD_CTRL_RES_DOWN BIT(14) +#define I2C_PAD_CTRL_RES_UP BIT(15) +#define I2C_PAD_CTRL_BIOS_CRT_EN BIT(16) +#define I2C_PAD_CTRL_SPARE0 BIT(17) +#define I2C_PAD_CTRL_SPARE1 BIT(18)
/* FCH AOAC Registers 0xfed81e00 */ #define FCH_AOAC_D3_CONTROL_CLK_GEN 0x40 -#define FCH_AOAC_D3_CONTROL_I2C0 0x4a -#define FCH_AOAC_D3_CONTROL_I2C1 0x4c #define FCH_AOAC_D3_CONTROL_I2C2 0x4e #define FCH_AOAC_D3_CONTROL_I2C3 0x50 +#define FCH_AOAC_D3_CONTROL_I2C4 0x52 #define FCH_AOAC_D3_CONTROL_UART0 0x56 #define FCH_AOAC_D3_CONTROL_UART1 0x58 #define FCH_AOAC_D3_CONTROL_AMBA 0x62 @@ -198,10 +223,9 @@ #define FCH_AOAC_IS_SW_CONTROL BIT(7)
#define FCH_AOAC_D3_STATE_CLK_GEN 0x41 -#define FCH_AOAC_D3_STATE_I2C0 0x4b -#define FCH_AOAC_D3_STATE_I2C1 0x4d #define FCH_AOAC_D3_STATE_I2C2 0x4f #define FCH_AOAC_D3_STATE_I2C3 0x51 +#define FCH_AOAC_D3_STATE_I2C4 0x53 #define FCH_AOAC_D3_STATE_UART0 0x57 #define FCH_AOAC_D3_STATE_UART1 0x59 #define FCH_AOAC_D3_STATE_AMBA 0x63 @@ -289,12 +313,11 @@ };
typedef struct aoac_devs { - unsigned int :5; - unsigned int ic0e:1; /* 5: I2C0 */ - unsigned int ic1e:1; /* 6: I2C1 */ + unsigned int :7; unsigned int ic2e:1; /* 7: I2C2 */ unsigned int ic3e:1; /* 8: I2C3 */ - unsigned int :2; + unsigned int ic4e:1; /* 9: I2C4 */ + unsigned int :1; unsigned int ut0e:1; /* 11: UART0 */ unsigned int ut1e:1; /* 12: UART1 */ unsigned int :2; @@ -370,4 +393,7 @@ /* Initialize all the i2c buses that are not marked with early init. */ void i2c_soc_init(void);
+/* Allow the board to change the default I2C pad configuration */ +void mainboard_i2c_override(int bus, uint32_t *pad_settings); + #endif /* __PICASSO_SB_H__ */ diff --git a/src/soc/amd/picasso/southbridge.c b/src/soc/amd/picasso/southbridge.c index e1d16b7..582034a 100644 --- a/src/soc/amd/picasso/southbridge.c +++ b/src/soc/amd/picasso/southbridge.c @@ -46,10 +46,9 @@ { (FCH_AOAC_D3_CONTROL_UART0 + CONFIG_UART_FOR_CONSOLE * 2), (FCH_AOAC_D3_STATE_UART0 + CONFIG_UART_FOR_CONSOLE * 2) }, { FCH_AOAC_D3_CONTROL_AMBA, FCH_AOAC_D3_STATE_AMBA }, - { FCH_AOAC_D3_CONTROL_I2C0, FCH_AOAC_D3_STATE_I2C0 }, - { FCH_AOAC_D3_CONTROL_I2C1, FCH_AOAC_D3_STATE_I2C1 }, { FCH_AOAC_D3_CONTROL_I2C2, FCH_AOAC_D3_STATE_I2C2 }, - { FCH_AOAC_D3_CONTROL_I2C3, FCH_AOAC_D3_STATE_I2C3 } + { FCH_AOAC_D3_CONTROL_I2C3, FCH_AOAC_D3_STATE_I2C3 }, + { FCH_AOAC_D3_CONTROL_I2C4, FCH_AOAC_D3_STATE_I2C4 } };
/* @@ -514,10 +513,9 @@ if (gnvs == NULL) return;
- gnvs->aoac.ic0e = is_aoac_device_enabled(FCH_AOAC_D3_STATE_I2C0); - gnvs->aoac.ic1e = is_aoac_device_enabled(FCH_AOAC_D3_STATE_I2C1); gnvs->aoac.ic2e = is_aoac_device_enabled(FCH_AOAC_D3_STATE_I2C2); gnvs->aoac.ic3e = is_aoac_device_enabled(FCH_AOAC_D3_STATE_I2C3); + gnvs->aoac.ic4e = is_aoac_device_enabled(FCH_AOAC_D3_STATE_I2C4); gnvs->aoac.ut0e = is_aoac_device_enabled(FCH_AOAC_D3_STATE_UART0); gnvs->aoac.ut1e = is_aoac_device_enabled(FCH_AOAC_D3_STATE_UART1); /* Rely on these being in sync with devicetree */
-
Marshall Dawson (Code Review) -
Martin Roth (Code Review)