Change in coreboot[master]: soc/amd/common/include/espi: generalize IO/MMIO decode range macros

[Felix Held (Code Review)]

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/64052 )

Change subject: soc/amd/common/include/espi: generalize IO/MMIO decode range macros
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soc/amd/common/include/espi: generalize IO/MMIO decode range macros

Sabrina has more eSPI decode ranges than Picasso or Cezanne. Those
registers are however not in one block where it's easy to calculate the
addresses of a register from the index of the decode range. Within one
group of decode range registers it's still easy to calculate the
register address, so move the base address from within the macro to the
instantiation of the macro as a preparation for adding the support for
the additional ranges.

TEST=Timeless build results in identical binary for Mandolin

Signed-off-by: Felix Held 
Change-Id: Id309d955fa3558d660db37a2075240f938361e83
---
M src/soc/amd/common/block/include/amdblocks/espi.h
M src/soc/amd/common/block/lpc/espi_util.c
2 files changed, 8 insertions(+), 8 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/64052/1

diff --git a/src/soc/amd/common/block/include/amdblocks/espi.h b/src/soc/amd/common/block/include/amdblocks/espi.h
index cfba50b..45a220e 100644
--- a/src/soc/amd/common/block/include/amdblocks/espi.h
+++ b/src/soc/amd/common/block/include/amdblocks/espi.h
@@ -25,10 +25,10 @@
 #define ESPI_MMIO_SIZE_REG0			0x60
 #define ESPI_MMIO_SIZE_REG1			0x64

-#define ESPI_IO_RANGE_BASE(range)		(ESPI_IO_BASE_REG0 + ((range) & 3) * 2)
-#define ESPI_IO_RANGE_SIZE(range)		(ESPI_IO_SIZE0 + ((range) & 3))
-#define ESPI_MMIO_RANGE_BASE(range)		(ESPI_MMIO_BASE_REG0 + ((range) & 3) * 4)
-#define ESPI_MMIO_RANGE_SIZE(range)		(ESPI_MMIO_SIZE_REG0 + ((range) & 3) * 2)
+#define ESPI_IO_RANGE_BASE_REG(base, range)	((base) + ((range) & 3) * 2)
+#define ESPI_IO_RANGE_SIZE_REG(base, range)	((base) + ((range) & 3))
+#define ESPI_MMIO_RANGE_BASE_REG(base, range)	((base) + ((range) & 3) * 4)
+#define ESPI_MMIO_RANGE_SIZE_REG(base, range)	((base) + ((range) & 3) * 2)

#define ESPI_GENERIC_IO_WIN_COUNT		4
 #define ESPI_GENERIC_IO_MAX_WIN_SIZE		0x100
diff --git a/src/soc/amd/common/block/lpc/espi_util.c b/src/soc/amd/common/block/lpc/espi_util.c
index c4d15e4..a5f43f4 100644
--- a/src/soc/amd/common/block/lpc/espi_util.c
+++ b/src/soc/amd/common/block/lpc/espi_util.c
@@ -72,22 +72,22 @@

static inline unsigned int espi_io_range_base_reg(unsigned int idx)
 {
-	return ESPI_IO_RANGE_BASE(idx);
+	return ESPI_IO_RANGE_BASE_REG(ESPI_IO_BASE_REG0, idx);
 }

static inline unsigned int espi_io_range_size_reg(unsigned int idx)
 {
-	return ESPI_IO_RANGE_SIZE(idx);
+	return ESPI_IO_RANGE_SIZE_REG(ESPI_IO_SIZE0, idx);
 }

static inline unsigned int espi_mmio_range_base_reg(unsigned int idx)
 {
-	return ESPI_MMIO_RANGE_BASE(idx);
+	return ESPI_MMIO_RANGE_BASE_REG(ESPI_MMIO_BASE_REG0, idx);
 }

static inline unsigned int espi_mmio_range_size_reg(unsigned int idx)
 {
-	return ESPI_MMIO_RANGE_SIZE(idx);
+	return ESPI_MMIO_RANGE_SIZE_REG(ESPI_MMIO_SIZE_REG0, idx);
 }

static void espi_enable_decode(uint32_t decode_en)