Attention is currently required from: Anjaneya "Reddy" Chagam, Subrata Banik, Jonathan Zhang, Johnny Lin, Tim Wawrzynczak, Christian Walter, Arthur Heymans, Andrey Petrov, Patrick Rudolph, Tim Chu. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61431 )
Change subject: soc/intel/common/cse: Rework heci_disable function ......................................................................
Patch Set 4:
(8 comments)
File src/soc/intel/common/block/cse/Kconfig:
https://review.coreboot.org/c/coreboot/+/61431/comment/cd5bc5a7_7a4e7d7c PS3, Line 22: only done nit: only be done
https://review.coreboot.org/c/coreboot/+/61431/comment/dce2510e_ceb2090b PS3, Line 25: make : HECI nit: make the HECI function in the SMM mode
https://review.coreboot.org/c/coreboot/+/61431/comment/a78ef339_6a6569a9 PS3, Line 22: From CNL PCH onwards,`HECI1` disabling can only done using : non-posted sideband write after FSP-S sets the postboot_sai : attribute. : Use this config to include common CSE block to make : HECI function disable in SMM mod Reordering of statements may require, something like below..
Use this config to allow common CSE block to make HECI1 function disable in the SMM mode. From CNL PCH onwards,`HECI1` disabling can only be done using the non-posted sideband write after FSP-S sets the postboot_sai attribute.
https://review.coreboot.org/c/coreboot/+/61431/comment/d2848b25_af3fe907 PS3, Line 43: Prior to postboot_sai enforcement since CNL PCH, `HECI1` device were : disable using private configuration register (PCR) write. Disable HECI1 device using the Private Configuration Register (PCR) write prior to enforcement of postboot_sai. This mechanism is available starting from CNL PCH.
File src/soc/intel/common/block/cse/disable_heci.c:
https://review.coreboot.org/c/coreboot/+/61431/comment/4d03abce_5e3c1121 PS3, Line 23: heci nit:heci1?
https://review.coreboot.org/c/coreboot/+/61431/comment/7b12da48_a0f9dd8c PS3, Line 64: heci_disable This disables only heci1 interface so this should be named as heci1_disable?
File src/soc/intel/common/block/include/intelblocks/cse.h:
https://review.coreboot.org/c/coreboot/+/61431/comment/169bdad3_1feff7f8 PS3, Line 493: PCR PCR.
https://review.coreboot.org/c/coreboot/+/61431/comment/793b463d_d062fe16 PS3, Line 494: PSF port id for disabling cse is expected to be different between : * SoC generation hence, allow SoC to implement the override. It may need rephrasing...