Marc Jones has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46971 )
Change subject: soc/intel/xeon_sp; Use soc specific stack-port function ......................................................................
soc/intel/xeon_sp; Use soc specific stack-port function
Separate the get_stack_for_port into soc specific functions. This removes a #if in common code.
Change-Id: Ib38a7d66947ded9b56193a9163e5128b2523e99c Signed-off-by: Marc Jones marcjones@sysproconsulting.com --- M src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h M src/soc/intel/xeon_sp/cpx/soc_util.c M src/soc/intel/xeon_sp/nb_acpi.c M src/soc/intel/xeon_sp/skx/include/soc/soc_util.h M src/soc/intel/xeon_sp/skx/soc_util.c 5 files changed, 51 insertions(+), 43 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/46971/1
diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h b/src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h index f0c2575..5f4a6f9 100644 --- a/src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h +++ b/src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h @@ -26,5 +26,6 @@ const struct SystemMemoryMapHob *get_system_memory_map(void);
void set_bios_init_completion(void); +int soc_get_stack_for_port(int port);
#endif /* _SOC_UTIL_H_ */ diff --git a/src/soc/intel/xeon_sp/cpx/soc_util.c b/src/soc/intel/xeon_sp/cpx/soc_util.c index bc4a1e1..de6d852 100644 --- a/src/soc/intel/xeon_sp/cpx/soc_util.c +++ b/src/soc/intel/xeon_sp/cpx/soc_util.c @@ -319,3 +319,25 @@ /* And finally, take care of the SBSP */ set_bios_init_completion_for_package(sbsp_socket_id); } +/* + * EX: CPX-SP + * Ports Stack Stack(HOB) IioConfigIou + * ========================================== + * 0 CSTACK stack 0 IOU0 + * 1A..1D PSTACKZ stack 1 IOU1 + * 2A..2D PSTACK1 stack 2 IOU2 + * 3A..3D PSTACK2 stack 4 IOU3 + */ +int soc_get_stack_for_port(int port) +{ + if (port == PORT_0) + return CSTACK; + else if (port >= PORT_1A && port <= PORT_1D) + return PSTACK0; + else if (port >= PORT_2A && port <= PORT_2D) + return PSTACK1; + else if (port >= PORT_3A && port <= PORT_3D) + return PSTACK2; + else + return -1; +} diff --git a/src/soc/intel/xeon_sp/nb_acpi.c b/src/soc/intel/xeon_sp/nb_acpi.c index 5955fa0..f6bf6ed 100644 --- a/src/soc/intel/xeon_sp/nb_acpi.c +++ b/src/soc/intel/xeon_sp/nb_acpi.c @@ -143,48 +143,6 @@ }
/* - * EX: CPX-SP - * Ports Stack Stack(HOB) IioConfigIou - * ========================================== - * 0 CSTACK stack 0 IOU0 - * 1A..1D PSTACKZ stack 1 IOU1 - * 2A..2D PSTACK1 stack 2 IOU2 - * 3A..3D PSTACK2 stack 4 IOU3 - */ -static int get_stack_for_port(int port) -{ -#if (CONFIG(SOC_INTEL_COOPERLAKE_SP)) - if (port == PORT_0) - return CSTACK; - else if (port >= PORT_1A && port <= PORT_1D) - return PSTACK0; - else if (port >= PORT_2A && port <= PORT_2D) - return PSTACK1; - else if (port >= PORT_3A && port <= PORT_3D) - return PSTACK2; - else - return -1; -#endif /* SOC_INTEL_COOPERLAKE_SP */ - -#if (CONFIG(SOC_INTEL_SKYLAKE_SP)) - if (port == PORT_0) - return CSTACK; - else if (port >= PORT_1A && port <= PORT_1D) - return PSTACK0; - else if (port >= PORT_2A && port <= PORT_2D) - return PSTACK1; - else if (port >= PORT_3A && port <= PORT_3D) - return PSTACK2; - else if (port >= PORT_4A && port <= PORT_4D) - return PSTACK3; // MCP0 - else if (port >= PORT_5A && port <= PORT_5D) - return PSTACK4; // MCP1 - else - return -1; -#endif /* SOC_INTEL_SKYLAKE_SP */ -} - -/* * This function adds PCIe bridge device entry in DMAR table. If it is called * in the context of ATSR subtable, it adds ATSR subtable when it is first called. */ @@ -193,7 +151,7 @@ bool is_atsr, bool *first) {
- if (get_stack_for_port(port) != stack) + if (soc_get_stack_for_port(port) != stack) return 0;
const uint32_t bus = iio_resource.StackRes[stack].BusBase; diff --git a/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h b/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h index 2566830..cce542a 100644 --- a/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h +++ b/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h @@ -27,5 +27,6 @@
void set_bios_init_completion(void); unsigned int soc_get_num_cpus(void); +int soc_get_stack_for_port(int port);
#endif /* _SOC_UTIL_H_ */ diff --git a/src/soc/intel/xeon_sp/skx/soc_util.c b/src/soc/intel/xeon_sp/skx/soc_util.c index 7dd954f..5c9c3ad 100644 --- a/src/soc/intel/xeon_sp/skx/soc_util.c +++ b/src/soc/intel/xeon_sp/skx/soc_util.c @@ -394,4 +394,30 @@ } }
+/* + * EX: CPX-SP + * Ports Stack Stack(HOB) IioConfigIou + * ========================================== + * 0 CSTACK stack 0 IOU0 + * 1A..1D PSTACKZ stack 1 IOU1 + * 2A..2D PSTACK1 stack 2 IOU2 + * 3A..3D PSTACK2 stack 4 IOU3 + */ +int soc_get_stack_for_port(int port) +{ + if (port == PORT_0) + return CSTACK; + else if (port >= PORT_1A && port <= PORT_1D) + return PSTACK0; + else if (port >= PORT_2A && port <= PORT_2D) + return PSTACK1; + else if (port >= PORT_3A && port <= PORT_3D) + return PSTACK2; + else if (port >= PORT_4A && port <= PORT_4D) + return PSTACK3; // MCP0 + else if (port >= PORT_5A && port <= PORT_5D) + return PSTACK4; // MCP1 + else + return -1; +} #endif
Stefan Reinauer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46971 )
Change subject: soc/intel/xeon_sp; Use soc specific stack-port function ......................................................................
Patch Set 1: Code-Review+2
(1 comment)
https://review.coreboot.org/c/coreboot/+/46971/1/src/soc/intel/xeon_sp/skx/s... File src/soc/intel/xeon_sp/skx/soc_util.c:
https://review.coreboot.org/c/coreboot/+/46971/1/src/soc/intel/xeon_sp/skx/s... PS1, Line 415: : else if (port >= PORT_4A && port <= PORT_4D) : return PSTACK3; // MCP0 : else if (port >= PORT_5A && port <= PORT_5D) : return PSTACK4; // MCP1 I know this is a refactor, but it would be good to document these.
Hello build bot (Jenkins), Stefan Reinauer, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46971
to look at the new patch set (#2).
Change subject: soc/intel/xeon_sp; Use soc specific stack-port function ......................................................................
soc/intel/xeon_sp; Use soc specific stack-port function
Separate the get_stack_for_port into soc specific functions. This removes a #if in common code.
Change-Id: Ib38a7d66947ded9b56193a9163e5128b2523e99c Signed-off-by: Marc Jones marcjones@sysproconsulting.com --- M src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h M src/soc/intel/xeon_sp/cpx/soc_util.c M src/soc/intel/xeon_sp/nb_acpi.c M src/soc/intel/xeon_sp/skx/include/soc/soc_util.h M src/soc/intel/xeon_sp/skx/soc_util.c 5 files changed, 53 insertions(+), 43 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/46971/2
Marc Jones has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46971 )
Change subject: soc/intel/xeon_sp; Use soc specific stack-port function ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/46971/1/src/soc/intel/xeon_sp/skx/s... File src/soc/intel/xeon_sp/skx/soc_util.c:
https://review.coreboot.org/c/coreboot/+/46971/1/src/soc/intel/xeon_sp/skx/s... PS1, Line 415: : else if (port >= PORT_4A && port <= PORT_4D) : return PSTACK3; // MCP0 : else if (port >= PORT_5A && port <= PORT_5D) : return PSTACK4; // MCP1
I know this is a refactor, but it would be good to document these.
Done
Stefan Reinauer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46971 )
Change subject: soc/intel/xeon_sp; Use soc specific stack-port function ......................................................................
Patch Set 2: Code-Review+2
Marc Jones has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46971 )
Change subject: soc/intel/xeon_sp; Use soc specific stack-port function ......................................................................
soc/intel/xeon_sp; Use soc specific stack-port function
Separate the get_stack_for_port into soc specific functions. This removes a #if in common code.
Change-Id: Ib38a7d66947ded9b56193a9163e5128b2523e99c Signed-off-by: Marc Jones marcjones@sysproconsulting.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/46971 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Stefan Reinauer stefan.reinauer@coreboot.org --- M src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h M src/soc/intel/xeon_sp/cpx/soc_util.c M src/soc/intel/xeon_sp/nb_acpi.c M src/soc/intel/xeon_sp/skx/include/soc/soc_util.h M src/soc/intel/xeon_sp/skx/soc_util.c 5 files changed, 53 insertions(+), 43 deletions(-)
Approvals: build bot (Jenkins): Verified Stefan Reinauer: Looks good to me, approved
diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h b/src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h index f0c2575..5f4a6f9 100644 --- a/src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h +++ b/src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h @@ -26,5 +26,6 @@ const struct SystemMemoryMapHob *get_system_memory_map(void);
void set_bios_init_completion(void); +int soc_get_stack_for_port(int port);
#endif /* _SOC_UTIL_H_ */ diff --git a/src/soc/intel/xeon_sp/cpx/soc_util.c b/src/soc/intel/xeon_sp/cpx/soc_util.c index bc4a1e1..de6d852 100644 --- a/src/soc/intel/xeon_sp/cpx/soc_util.c +++ b/src/soc/intel/xeon_sp/cpx/soc_util.c @@ -319,3 +319,25 @@ /* And finally, take care of the SBSP */ set_bios_init_completion_for_package(sbsp_socket_id); } +/* + * EX: CPX-SP + * Ports Stack Stack(HOB) IioConfigIou + * ========================================== + * 0 CSTACK stack 0 IOU0 + * 1A..1D PSTACKZ stack 1 IOU1 + * 2A..2D PSTACK1 stack 2 IOU2 + * 3A..3D PSTACK2 stack 4 IOU3 + */ +int soc_get_stack_for_port(int port) +{ + if (port == PORT_0) + return CSTACK; + else if (port >= PORT_1A && port <= PORT_1D) + return PSTACK0; + else if (port >= PORT_2A && port <= PORT_2D) + return PSTACK1; + else if (port >= PORT_3A && port <= PORT_3D) + return PSTACK2; + else + return -1; +} diff --git a/src/soc/intel/xeon_sp/nb_acpi.c b/src/soc/intel/xeon_sp/nb_acpi.c index 5955fa0..f6bf6ed 100644 --- a/src/soc/intel/xeon_sp/nb_acpi.c +++ b/src/soc/intel/xeon_sp/nb_acpi.c @@ -143,48 +143,6 @@ }
/* - * EX: CPX-SP - * Ports Stack Stack(HOB) IioConfigIou - * ========================================== - * 0 CSTACK stack 0 IOU0 - * 1A..1D PSTACKZ stack 1 IOU1 - * 2A..2D PSTACK1 stack 2 IOU2 - * 3A..3D PSTACK2 stack 4 IOU3 - */ -static int get_stack_for_port(int port) -{ -#if (CONFIG(SOC_INTEL_COOPERLAKE_SP)) - if (port == PORT_0) - return CSTACK; - else if (port >= PORT_1A && port <= PORT_1D) - return PSTACK0; - else if (port >= PORT_2A && port <= PORT_2D) - return PSTACK1; - else if (port >= PORT_3A && port <= PORT_3D) - return PSTACK2; - else - return -1; -#endif /* SOC_INTEL_COOPERLAKE_SP */ - -#if (CONFIG(SOC_INTEL_SKYLAKE_SP)) - if (port == PORT_0) - return CSTACK; - else if (port >= PORT_1A && port <= PORT_1D) - return PSTACK0; - else if (port >= PORT_2A && port <= PORT_2D) - return PSTACK1; - else if (port >= PORT_3A && port <= PORT_3D) - return PSTACK2; - else if (port >= PORT_4A && port <= PORT_4D) - return PSTACK3; // MCP0 - else if (port >= PORT_5A && port <= PORT_5D) - return PSTACK4; // MCP1 - else - return -1; -#endif /* SOC_INTEL_SKYLAKE_SP */ -} - -/* * This function adds PCIe bridge device entry in DMAR table. If it is called * in the context of ATSR subtable, it adds ATSR subtable when it is first called. */ @@ -193,7 +151,7 @@ bool is_atsr, bool *first) {
- if (get_stack_for_port(port) != stack) + if (soc_get_stack_for_port(port) != stack) return 0;
const uint32_t bus = iio_resource.StackRes[stack].BusBase; diff --git a/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h b/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h index 2566830..cce542a 100644 --- a/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h +++ b/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h @@ -27,5 +27,6 @@
void set_bios_init_completion(void); unsigned int soc_get_num_cpus(void); +int soc_get_stack_for_port(int port);
#endif /* _SOC_UTIL_H_ */ diff --git a/src/soc/intel/xeon_sp/skx/soc_util.c b/src/soc/intel/xeon_sp/skx/soc_util.c index 7dd954f..3af6483 100644 --- a/src/soc/intel/xeon_sp/skx/soc_util.c +++ b/src/soc/intel/xeon_sp/skx/soc_util.c @@ -394,4 +394,32 @@ } }
+/* + * EX: SKX-SP + * Ports Stack Stack(HOB) IioConfigIou + * ========================================== + * 0 CSTACK stack 0 IOU0 + * 1A..1D PSTACKZ stack 1 IOU1 + * 2A..2D PSTACK1 stack 2 IOU2 + * 3A..3D PSTACK2 stack 3 IOU3 + * 5A..4D PSTACK3 stack 4 IOU4 + * 5A..5D PSTACK4 stack 5 IOU5 + */ +int soc_get_stack_for_port(int port) +{ + if (port == PORT_0) + return CSTACK; + else if (port >= PORT_1A && port <= PORT_1D) + return PSTACK0; + else if (port >= PORT_2A && port <= PORT_2D) + return PSTACK1; + else if (port >= PORT_3A && port <= PORT_3D) + return PSTACK2; + else if (port >= PORT_4A && port <= PORT_4D) + return PSTACK3; // MCP0 + else if (port >= PORT_5A && port <= PORT_5D) + return PSTACK4; // MCP1 + else + return -1; +} #endif
-
Marc Jones (Code Review) -
Stefan Reinauer (Code Review)