[L] Change in coreboot[main]: soc/xeon_sp: Initially add IBL codes

[Patrick Rudolph (Code Review)]

Attention is currently required from: Arthur Heymans, Christian Walter, David Hendricks, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Shuo Liu, TangYiwei, Tim Chu.

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81315?usp=email )

Change subject: soc/xeon_sp: Initially add IBL codes
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Patch Set 6:

(2 comments)

Commit Message:

https://review.coreboot.org/c/coreboot/+/81315/comment/a45cfd19_d563616d :
PS6, Line 9: IBL
Please reference the intel documents used to write this code and give a short introduction what the different compared to PCH enabled platforms.
I guess it just contains the SPI controller, eSPI controller, P2SB device, HPET and IOAPIC?

File src/soc/intel/xeon_sp/ibl/include/soc/azalia_device.h:

https://review.coreboot.org/c/coreboot/+/81315/comment/460f2910_7eee3080 :
PS6, Line 3: DEVICE_AZALIA_H
there's an integrated HDA device?