[XS] Change in coreboot[main]: cpu/intel/model_206ax: Lock MSR_PP_CURRENT_CONFIG

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/78608?usp=email )

Change subject: cpu/intel/model_206ax: Lock MSR_PP_CURRENT_CONFIG
......................................................................

cpu/intel/model_206ax: Lock MSR_PP_CURRENT_CONFIG

Now that those registers are only written once set the lock bit to
protect it from runtime changes.

TEST: Lenovo X220 still boots.

Change-Id: I4c56a3cb322a0e75eb3dd366808068093928e10c
Signed-off-by: Patrick Rudolph 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78608
Tested-by: build bot (Jenkins) 
Reviewed-by: Arthur Heymans 
---
M src/cpu/intel/model_206ax/model_206ax.h
M src/cpu/intel/model_206ax/model_206ax_init.c
2 files changed, 4 insertions(+), 0 deletions(-)

Approvals:
  Arthur Heymans: Looks good to me, approved
  build bot (Jenkins): Verified

diff --git a/src/cpu/intel/model_206ax/model_206ax.h b/src/cpu/intel/model_206ax/model_206ax.h
index ecbf323..9379c29 100644
--- a/src/cpu/intel/model_206ax/model_206ax.h
+++ b/src/cpu/intel/model_206ax/model_206ax.h
@@ -73,8 +73,10 @@
 #define  PKG_POWER_LIMIT_TIME_MASK	0x7f

#define MSR_PP0_CURRENT_CONFIG		0x601
+#define  PP0_CURRENT_LIMIT_LOCK		(1U << 31)
 #define  PP0_CURRENT_LIMIT		(112 << 3) /* 112 A */
 #define MSR_PP1_CURRENT_CONFIG		0x602
+#define  PP1_CURRENT_LIMIT_LOCK		(1U << 31)
 #define  PP1_CURRENT_LIMIT_SNB		(35 << 3) /* 35 A */
 #define  PP1_CURRENT_LIMIT_IVB		(50 << 3) /* 50 A */
 #define MSR_PKG_POWER_SKU_UNIT		0x606
diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c
index 14a7965..dfe7ae5 100644
--- a/src/cpu/intel/model_206ax/model_206ax_init.c
+++ b/src/cpu/intel/model_206ax/model_206ax_init.c
@@ -206,6 +206,7 @@
    	msr = rdmsr(MSR_PP0_CURRENT_CONFIG);
    	msr.lo &= ~0x1fff;
    	msr.lo |= PP0_CURRENT_LIMIT;
+		msr.lo |= PP0_CURRENT_LIMIT_LOCK;
    	wrmsr(MSR_PP0_CURRENT_CONFIG, msr);

/* Secondary Plane Current Limit */
@@ -215,6 +216,7 @@
    		msr.lo |= PP1_CURRENT_LIMIT_IVB;
    	else
    		msr.lo |= PP1_CURRENT_LIMIT_SNB;
+		msr.lo |= PP1_CURRENT_LIMIT_LOCK;
    	wrmsr(MSR_PP1_CURRENT_CONFIG, msr);
    }
 }