[S] Change in coreboot[master]: cpu/amd/agesa/*/fixme.c: Drop some white space issues

[Martin L Roth (Code Review)]

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/65887 )

(

1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
 )Change subject: cpu/amd/agesa/*/fixme.c: Drop some white space issues
......................................................................

cpu/amd/agesa/*/fixme.c: Drop some white space issues

Signed-off-by: Elyes Haouas 
Change-Id: I335b5ac415b76067c70c8e2e6f1703eb10f69c50
---
M src/cpu/amd/agesa/family14/fixme.c
M src/cpu/amd/agesa/family16kb/fixme.c
2 files changed, 18 insertions(+), 8 deletions(-)

Approvals:
  Paul Menzel: Looks good to me, but someone else must approve
  Angel Pons: Looks good to me, approved
  build bot (Jenkins): Verified

diff --git a/src/cpu/amd/agesa/family14/fixme.c b/src/cpu/amd/agesa/family14/fixme.c
index 16caf40..4c16cc3 100644
--- a/src/cpu/amd/agesa/family14/fixme.c
+++ b/src/cpu/amd/agesa/family14/fixme.c
@@ -39,7 +39,7 @@
    LibAmdMsrRead(TOP_MEM, &MsrReg, &StdHeader);
    MsrReg = (MsrReg >> 8) | 3;
    PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x88);
-	PciData = (UINT32) MsrReg;
+	PciData = (UINT32)MsrReg;
    LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);

/* Send all IO (0000-FFFF) to southbridge. */
diff --git a/src/cpu/amd/agesa/family16kb/fixme.c b/src/cpu/amd/agesa/family16kb/fixme.c
index 5e43b17..2960f6e 100644
--- a/src/cpu/amd/agesa/family16kb/fixme.c
+++ b/src/cpu/amd/agesa/family16kb/fixme.c
@@ -16,7 +16,7 @@
    AMD_CONFIG_PARAMS             StdHeader;

/* Enable legacy video routing: D18F1xF4 VGA Enable */
-	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xF4);
+	PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xF4);
    PciData = 1;
    LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);

@@ -24,29 +24,29 @@
     * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are
     * set to non-posted regions.
     */
-	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84);
+	PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x84);
    PciData = 0x00FEDF00; /* last address before processor local APIC at FEE00000 */
    PciData |= 1 << 7;    /* set NP (non-posted) bit */
    LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80);
+	PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x80);
    PciData = (HPET_BASE_ADDRESS >> 8) | 3; /* lowest NP address is HPET at FED00000 */
    LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);

/* Map the remaining PCI hole as posted MMIO */
-	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C);
+	PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x8C);
    PciData = 0x00FECF00; /* last address before non-posted range */
    LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
    LibAmdMsrRead(TOP_MEM, &MsrReg, &StdHeader);
    MsrReg = (MsrReg >> 8) | 3;
-	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88);
+	PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x88);
    PciData = (UINT32)MsrReg;
    LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);

/* Send all IO (0000-FFFF) to southbridge. */
-	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC4);
+	PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC4);
    PciData = 0x0000F000;
    LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC0);
+	PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC0);
    PciData = 0x00000003;
    LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
 }