[S] Change in coreboot[main]: sb/intel/bd82x6x/pcie: Use defines

[Patrick Rudolph (Code Review)]

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/78293?usp=email )

Change subject: sb/intel/bd82x6x/pcie: Use defines
......................................................................

sb/intel/bd82x6x/pcie: Use defines

Use defines instead of magic values.

Test: Lenovo X220 still boots and all PCIe devices are
      still working.

Change-Id: Ie8fc7cc863017da07dd3ed37b487dae18de92b18
Signed-off-by: Patrick Rudolph 
---
M src/southbridge/intel/bd82x6x/pcie.c
1 file changed, 5 insertions(+), 5 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/78293/1

diff --git a/src/southbridge/intel/bd82x6x/pcie.c b/src/southbridge/intel/bd82x6x/pcie.c
index 599d5d9..965bc81 100644
--- a/src/southbridge/intel/bd82x6x/pcie.c
+++ b/src/southbridge/intel/bd82x6x/pcie.c
@@ -125,9 +125,11 @@
    reg32 &= ~(1 << 31); /* Disable PME# SCI for native PME handling */
    pci_write_config32(dev, 0xd8, reg32);

+	cap = pci_find_capability(dev, PCI_CAP_ID_PCIE);
+
    /* Adjust ASPM L1 exit latency */
-	reg32 = pci_read_config32(dev, 0x4c);
-	reg32 &= ~((1 << 17) | (1 << 16) | (1 << 15));
+	reg32 = pci_read_config32(dev, cap + PCI_EXP_LNKCAP);
+	reg32 &= ~PCI_EXP_LNKCAP_L1EL;
    if (RCBA32(CIR9) & (1 << 16)) {
    	/* If RCBA+2320[15]=1 set ASPM L1 to 8-16us */
    	reg32 |= (1 << 17);
@@ -135,11 +137,9 @@
    	/* Else set ASPM L1 to 2-4us */
    	reg32 |= (1 << 16);
    }
-	pci_write_config32(dev, 0x4c, reg32);
+	pci_write_config32(dev, cap + PCI_EXP_LNKCAP, reg32);

/* Set slot power limit as configured above */
-	cap = pci_find_capability(dev, PCI_CAP_ID_PCIE);
-
    reg32 = pci_read_config32(dev, cap + PCI_EXP_SLTCAP);
    if (pci_is_hotplugable(dev))
    	reg32 |= (PCI_EXP_SLTCAP_HPS | PCI_EXP_SLTCAP_HPC);