Change in coreboot[master]: soc/intel/common: Add enable PCH FIVR entry under GNVS

[Sumeet R Pawnikar (Code Review)]

Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58139 )

Change subject: soc/intel/common: Add enable PCH FIVR entry under GNVS
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soc/intel/common: Add enable PCH FIVR entry under GNVS

Add enable PCH FIVR entry under GNVS

Change-Id: I2345e61b6b7afabb8110dd1e9121cb084dadfa40
Signed-off-by: Sumeet Pawnikar 
---
M src/soc/intel/common/block/acpi/acpi/globalnvs.asl
M src/soc/intel/common/block/include/intelblocks/nvs.h
2 files changed, 2 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/58139/1

diff --git a/src/soc/intel/common/block/acpi/acpi/globalnvs.asl b/src/soc/intel/common/block/acpi/acpi/globalnvs.asl
index ab63a5c..a19c3a3 100644
--- a/src/soc/intel/common/block/acpi/acpi/globalnvs.asl
+++ b/src/soc/intel/common/block/acpi/acpi/globalnvs.asl
@@ -25,4 +25,5 @@
    A4GB,	64,	// 0x30 - 0x37 Base of above 4GB MMIO Resource
    A4GS,	64,	// 0x38 - 0x3f Length of above 4GB MMIO Resource
    ,	64, 	// 0x40 - 0x47 Hest log buffer (used in SMM, not ASL code)
+	PCHE,	8,	// 0x48 - Enable PCH FIVR
 }
diff --git a/src/soc/intel/common/block/include/intelblocks/nvs.h b/src/soc/intel/common/block/include/intelblocks/nvs.h
index 5adbdb8..5f1c0ee 100644
--- a/src/soc/intel/common/block/include/intelblocks/nvs.h
+++ b/src/soc/intel/common/block/include/intelblocks/nvs.h
@@ -27,6 +27,7 @@
    u64	a4gb; /* 0x30 - 0x37 Base of above 4GB MMIO Resource */
    u64	a4gs; /* 0x38 - 0x3f Length of above 4GB MMIO Resource */
    u64	hest_log_addr; /* 0x40 - 47 err log addr (used in SMM, not ASL code) */
+	u8	pche; /* 0x48 - Enable PCH FIVR */
 };

#endif