Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48765 )
Change subject: sb,soc/intel: Drop unnecessary headers ......................................................................
sb,soc/intel: Drop unnecessary headers
Files under sb/ or soc/ should not have includes that tie those directly to external components like ChromeEC os ChromeOS vendorcode.
Change-Id: Ib56eeedaa9d7422e221efa9c8480ed5e12024bca Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/lib/coreboot_table.c M src/mainboard/google/butterfly/early_init.c M src/soc/intel/baytrail/romstage/raminit.c M src/soc/intel/baytrail/romstage/romstage.c M src/soc/intel/broadwell/acpi.c M src/soc/intel/broadwell/cpu/acpi.c M src/soc/intel/broadwell/pch/acpi.c M src/soc/intel/broadwell/raminit.c M src/southbridge/intel/bd82x6x/me.c M src/southbridge/intel/bd82x6x/me_8.x.c 10 files changed, 0 insertions(+), 34 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/48765/1
diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index 996e76e..440c1c3 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -26,13 +26,6 @@ #if CONFIG(USE_OPTION_TABLE) #include <option_table.h> #endif -#if CONFIG(CHROMEOS) -#if CONFIG(HAVE_ACPI_TABLES) -#include <acpi/acpi.h> -#endif -#include <vendorcode/google/chromeos/chromeos.h> -#include <vendorcode/google/chromeos/gnvs.h> -#endif #if CONFIG(PLATFORM_USES_FSP2_0) #include <fsp/util.h> #else diff --git a/src/mainboard/google/butterfly/early_init.c b/src/mainboard/google/butterfly/early_init.c index 2ffa3aa..c439fe2 100644 --- a/src/mainboard/google/butterfly/early_init.c +++ b/src/mainboard/google/butterfly/early_init.c @@ -7,9 +7,6 @@ #include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> -#if CONFIG(CHROMEOS) -#include <vendorcode/google/chromeos/chromeos.h> -#endif
void mainboard_late_rcba_config(void) { diff --git a/src/soc/intel/baytrail/romstage/raminit.c b/src/soc/intel/baytrail/romstage/raminit.c index 10ad932..f922750 100644 --- a/src/soc/intel/baytrail/romstage/raminit.c +++ b/src/soc/intel/baytrail/romstage/raminit.c @@ -17,8 +17,6 @@ #include <soc/iosf.h> #include <soc/pci_devs.h> #include <soc/romstage.h> -#include <ec/google/chromeec/ec.h> -#include <ec/google/chromeec/ec_commands.h> #include <security/vboot/vboot_common.h>
uintptr_t smbus_base(void) diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index 76aa711..b0d380c 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -6,9 +6,6 @@ #include <device/pci_ops.h> #include <console/console.h> #include <cbmem.h> -#if CONFIG(EC_GOOGLE_CHROMEEC) -#include <ec/google/chromeec/ec.h> -#endif #include <elog.h> #include <romstage_handoff.h> #include <string.h> diff --git a/src/soc/intel/broadwell/acpi.c b/src/soc/intel/broadwell/acpi.c index 9b5ac9e..dbaade6 100644 --- a/src/soc/intel/broadwell/acpi.c +++ b/src/soc/intel/broadwell/acpi.c @@ -14,8 +14,6 @@ #include <arch/cpu.h> #include <cpu/x86/msr.h> #include <cpu/intel/turbo.h> -#include <ec/google/chromeec/ec.h> -#include <vendorcode/google/chromeos/gnvs.h> #include <soc/acpi.h> #include <soc/cpu.h> #include <soc/iomap.h> diff --git a/src/soc/intel/broadwell/cpu/acpi.c b/src/soc/intel/broadwell/cpu/acpi.c index ec3d588..23f674b 100644 --- a/src/soc/intel/broadwell/cpu/acpi.c +++ b/src/soc/intel/broadwell/cpu/acpi.c @@ -14,8 +14,6 @@ #include <arch/cpu.h> #include <cpu/x86/msr.h> #include <cpu/intel/turbo.h> -#include <ec/google/chromeec/ec.h> -#include <vendorcode/google/chromeos/gnvs.h> #include <soc/acpi.h> #include <soc/cpu.h> #include <soc/iomap.h> diff --git a/src/soc/intel/broadwell/pch/acpi.c b/src/soc/intel/broadwell/pch/acpi.c index 712bb46..34f9c04 100644 --- a/src/soc/intel/broadwell/pch/acpi.c +++ b/src/soc/intel/broadwell/pch/acpi.c @@ -14,8 +14,6 @@ #include <arch/cpu.h> #include <cpu/x86/msr.h> #include <cpu/intel/turbo.h> -#include <ec/google/chromeec/ec.h> -#include <vendorcode/google/chromeos/gnvs.h> #include <soc/acpi.h> #include <soc/cpu.h> #include <soc/iomap.h> diff --git a/src/soc/intel/broadwell/raminit.c b/src/soc/intel/broadwell/raminit.c index 44a8937..506c6f6 100644 --- a/src/soc/intel/broadwell/raminit.c +++ b/src/soc/intel/broadwell/raminit.c @@ -9,11 +9,6 @@ #include <memory_info.h> #include <mrc_cache.h> #include <string.h> -#if CONFIG(EC_GOOGLE_CHROMEEC) -#include <ec/google/chromeec/ec.h> -#include <ec/google/chromeec/ec_commands.h> -#endif -#include <vendorcode/google/chromeos/chromeos.h> #include <soc/iomap.h> #include <soc/pei_data.h> #include <soc/pei_wrapper.h> diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c index 3876b02..2adfbd5 100644 --- a/src/southbridge/intel/bd82x6x/me.c +++ b/src/southbridge/intel/bd82x6x/me.c @@ -23,10 +23,6 @@ #include "me.h" #include "pch.h"
-#if CONFIG(CHROMEOS) -#include <vendorcode/google/chromeos/gnvs.h> -#endif - /* Send END OF POST message to the ME */ static int __unused mkhi_end_of_post(void) { diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c index d47c1da..b0226a6 100644 --- a/src/southbridge/intel/bd82x6x/me_8.x.c +++ b/src/southbridge/intel/bd82x6x/me_8.x.c @@ -23,10 +23,6 @@ #include "me.h" #include "pch.h"
-#if CONFIG(CHROMEOS) -#include <vendorcode/google/chromeos/gnvs.h> -#endif - /* Send END OF POST message to the ME */ static int __unused mkhi_end_of_post(void) {
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48765 )
Change subject: sb,soc/intel: Drop unnecessary headers ......................................................................
Patch Set 1: Code-Review+2
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48765 )
Change subject: sb,soc/intel: Drop unnecessary headers ......................................................................
Patch Set 1: Code-Review+2
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48765 )
Change subject: sb,soc/intel: Drop unnecessary headers ......................................................................
Patch Set 2: Code-Review+2
Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48765 )
Change subject: sb,soc/intel: Drop unnecessary headers ......................................................................
sb,soc/intel: Drop unnecessary headers
Files under sb/ or soc/ should not have includes that tie those directly to external components like ChromeEC os ChromeOS vendorcode.
Change-Id: Ib56eeedaa9d7422e221efa9c8480ed5e12024bca Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/48765 Reviewed-by: Michael Niewöhner foss@mniewoehner.de Reviewed-by: Patrick Rudolph siro@das-labor.org Reviewed-by: Angel Pons th3fanbus@gmail.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/lib/coreboot_table.c M src/mainboard/google/butterfly/early_init.c M src/soc/intel/baytrail/romstage/raminit.c M src/soc/intel/baytrail/romstage/romstage.c M src/soc/intel/broadwell/acpi.c M src/soc/intel/broadwell/cpu/acpi.c M src/soc/intel/broadwell/pch/acpi.c M src/soc/intel/broadwell/raminit.c M src/southbridge/intel/bd82x6x/me.c M src/southbridge/intel/bd82x6x/me_8.x.c 10 files changed, 0 insertions(+), 34 deletions(-)
Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved Angel Pons: Looks good to me, approved Michael Niewöhner: Looks good to me, approved
diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index 9e0d589..d6fd84a 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -27,13 +27,6 @@ #if CONFIG(USE_OPTION_TABLE) #include <option_table.h> #endif -#if CONFIG(CHROMEOS) -#if CONFIG(HAVE_ACPI_TABLES) -#include <acpi/acpi.h> -#endif -#include <vendorcode/google/chromeos/chromeos.h> -#include <vendorcode/google/chromeos/gnvs.h> -#endif #if CONFIG(PLATFORM_USES_FSP2_0) #include <fsp/util.h> #else diff --git a/src/mainboard/google/butterfly/early_init.c b/src/mainboard/google/butterfly/early_init.c index 2ffa3aa..c439fe2 100644 --- a/src/mainboard/google/butterfly/early_init.c +++ b/src/mainboard/google/butterfly/early_init.c @@ -7,9 +7,6 @@ #include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> -#if CONFIG(CHROMEOS) -#include <vendorcode/google/chromeos/chromeos.h> -#endif
void mainboard_late_rcba_config(void) { diff --git a/src/soc/intel/baytrail/romstage/raminit.c b/src/soc/intel/baytrail/romstage/raminit.c index 10ad932..f922750 100644 --- a/src/soc/intel/baytrail/romstage/raminit.c +++ b/src/soc/intel/baytrail/romstage/raminit.c @@ -17,8 +17,6 @@ #include <soc/iosf.h> #include <soc/pci_devs.h> #include <soc/romstage.h> -#include <ec/google/chromeec/ec.h> -#include <ec/google/chromeec/ec_commands.h> #include <security/vboot/vboot_common.h>
uintptr_t smbus_base(void) diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index 76aa711..b0d380c 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -6,9 +6,6 @@ #include <device/pci_ops.h> #include <console/console.h> #include <cbmem.h> -#if CONFIG(EC_GOOGLE_CHROMEEC) -#include <ec/google/chromeec/ec.h> -#endif #include <elog.h> #include <romstage_handoff.h> #include <string.h> diff --git a/src/soc/intel/broadwell/acpi.c b/src/soc/intel/broadwell/acpi.c index 9b5ac9e..dbaade6 100644 --- a/src/soc/intel/broadwell/acpi.c +++ b/src/soc/intel/broadwell/acpi.c @@ -14,8 +14,6 @@ #include <arch/cpu.h> #include <cpu/x86/msr.h> #include <cpu/intel/turbo.h> -#include <ec/google/chromeec/ec.h> -#include <vendorcode/google/chromeos/gnvs.h> #include <soc/acpi.h> #include <soc/cpu.h> #include <soc/iomap.h> diff --git a/src/soc/intel/broadwell/cpu/acpi.c b/src/soc/intel/broadwell/cpu/acpi.c index ec3d588..23f674b 100644 --- a/src/soc/intel/broadwell/cpu/acpi.c +++ b/src/soc/intel/broadwell/cpu/acpi.c @@ -14,8 +14,6 @@ #include <arch/cpu.h> #include <cpu/x86/msr.h> #include <cpu/intel/turbo.h> -#include <ec/google/chromeec/ec.h> -#include <vendorcode/google/chromeos/gnvs.h> #include <soc/acpi.h> #include <soc/cpu.h> #include <soc/iomap.h> diff --git a/src/soc/intel/broadwell/pch/acpi.c b/src/soc/intel/broadwell/pch/acpi.c index 712bb46..34f9c04 100644 --- a/src/soc/intel/broadwell/pch/acpi.c +++ b/src/soc/intel/broadwell/pch/acpi.c @@ -14,8 +14,6 @@ #include <arch/cpu.h> #include <cpu/x86/msr.h> #include <cpu/intel/turbo.h> -#include <ec/google/chromeec/ec.h> -#include <vendorcode/google/chromeos/gnvs.h> #include <soc/acpi.h> #include <soc/cpu.h> #include <soc/iomap.h> diff --git a/src/soc/intel/broadwell/raminit.c b/src/soc/intel/broadwell/raminit.c index 44a8937..506c6f6 100644 --- a/src/soc/intel/broadwell/raminit.c +++ b/src/soc/intel/broadwell/raminit.c @@ -9,11 +9,6 @@ #include <memory_info.h> #include <mrc_cache.h> #include <string.h> -#if CONFIG(EC_GOOGLE_CHROMEEC) -#include <ec/google/chromeec/ec.h> -#include <ec/google/chromeec/ec_commands.h> -#endif -#include <vendorcode/google/chromeos/chromeos.h> #include <soc/iomap.h> #include <soc/pei_data.h> #include <soc/pei_wrapper.h> diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c index 3876b02..2adfbd5 100644 --- a/src/southbridge/intel/bd82x6x/me.c +++ b/src/southbridge/intel/bd82x6x/me.c @@ -23,10 +23,6 @@ #include "me.h" #include "pch.h"
-#if CONFIG(CHROMEOS) -#include <vendorcode/google/chromeos/gnvs.h> -#endif - /* Send END OF POST message to the ME */ static int __unused mkhi_end_of_post(void) { diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c index d47c1da..b0226a6 100644 --- a/src/southbridge/intel/bd82x6x/me_8.x.c +++ b/src/southbridge/intel/bd82x6x/me_8.x.c @@ -23,10 +23,6 @@ #include "me.h" #include "pch.h"
-#if CONFIG(CHROMEOS) -#include <vendorcode/google/chromeos/gnvs.h> -#endif - /* Send END OF POST message to the ME */ static int __unused mkhi_end_of_post(void) {