[S] Change in coreboot[master]: soc/amd/phoenix/chipset.cb: add missing GPP bridges on device 1

[Felix Held (Code Review)]

Attention is currently required from: Jason Glenesk, Martin Roth, Felix Held.

Hello build bot (Jenkins), Jason Glenesk, Matt DeVillier, Fred Reitberger,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/72736

to look at the new patch set (#4).

Change subject: soc/amd/phoenix/chipset.cb: add missing GPP bridges on device 1
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soc/amd/phoenix/chipset.cb: add missing GPP bridges on device 1

Only the PCIe ports on the functions of device 2 were present in the
devicetree and had the amd_external_pcie_gpp_ops ops assigned. Add the
missing PCIe ports on the functions of device 1 and assign the
amd_external_pcie_gpp_ops ops to them.

This SoC uses a slightly different naming scheme for its PCIe GPP ports.
Previously the PCIe GPP bridge number from the PCI Device ID Assignments
table from the PPR was used. Those bridge numbers are one less than the
function numbers of the device. This is due to function 0 being a dummy
bridge to avoid having to shuffle around the function numbers when the
first bridge is unused, since the PCIe specification mandates the
function 0 to be implemented if any other function on the same device is
implemented. In order for the device aliases to be consistent with the
PCIe device and function numbers which is way more commonly used and
also what lspci shows and what goes into the DXIO descriptors, change
the naming scheme of the aliases.

This was checked with PPR #57019 Rev 1.65 and PPR #57396 Rev 1.54.

Signed-off-by: Felix Held 
Change-Id: Ib5c62c1df585877d9b6986a462a3636d4f2eb4c7
---
M src/soc/amd/phoenix/chipset.cb
1 file changed, 35 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/72736/4