[S] Change in coreboot[main]: [Do Not Merge] mb/google/brya/variants/trulo: ish pin mapping for trulo

[Dinesh Gehlot (Code Review)]

Dinesh Gehlot has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84151?usp=email )

Change subject: [Do Not Merge] mb/google/brya/variants/trulo: ish pin mapping for trulo
......................................................................

[Do Not Merge] mb/google/brya/variants/trulo: ish pin mapping for trulo

Change-Id: Ia4aaaa27d8a60ca9972f99b32597eef386cc365e
Signed-off-by: Dinesh Gehlot 
---
M src/mainboard/google/brya/variants/trulo/gpio.c
1 file changed, 10 insertions(+), 10 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/84151/1

diff --git a/src/mainboard/google/brya/variants/trulo/gpio.c b/src/mainboard/google/brya/variants/trulo/gpio.c
index 1651b08..63a5086 100644
--- a/src/mainboard/google/brya/variants/trulo/gpio.c
+++ b/src/mainboard/google/brya/variants/trulo/gpio.c
@@ -34,8 +34,8 @@
    PAD_NC(GPP_A14, NONE),
    /* A15 : USB_OC2# ==> NC */
    PAD_NC(GPP_A15, NONE),
-	/* A16 : USB_OC3# ==> NC */
-	PAD_NC_LOCK(GPP_A16, NONE, LOCK_CONFIG),
+	/* A16 : [NF1: USB_OC3# NF4: ISH_GP5 NF6: USB_C_GPP_A16] ==> ISH_MODE_ANGLE_2 */
+	PAD_CFG_NF(GPP_A16, NONE, DEEP, NF4),
    /* A17 : GPP_A17 ==> GSC_SOC_INT_ODL */
    PAD_CFG_GPI_APIC(GPP_A17, NONE, PLTRST, LEVEL, INVERT),
    /* A18 : DDSP_HPDB ==> DDI2_HPD */
@@ -117,14 +117,14 @@
    /* C7  : SML1_SMBDATA */
    PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1),

-	/* D0  : ISH_GP0 ==> SOC_GSEN1_INT# */
+	/* D0 : [NF1: ISH_GP0 NF2: BK0 NF5: SBK0 NF6: USB_C_GPP_D0] ==> SOC_GSEN1_INT# */
    PAD_CFG_NF(GPP_D0, NONE, DEEP, NF1),
-	/* D1  : ISH_GP1 ==> SOC_GSEN2_INT# */
+	/* D1 : [NF1: ISH_GP1 NF2: BK1 NF5: SBK1 NF6: USB_C_GPP_D1] ==> SOC_GSEN2_INT# */
    PAD_CFG_NF(GPP_D1, NONE, DEEP, NF1),
-	/* D2  : ISH_GP2 ==> SEN_MODE_EC_PCH_INT_ODL */
-	PAD_CFG_GPI_LOCK(GPP_D2, NONE, LOCK_CONFIG),
-	/* D3  : NC */
-	PAD_NC_LOCK(GPP_D3, NONE, LOCK_CONFIG),
+	/* D2 : [NF1: ISH_GP2 NF2: BK2 NF5: SBK2 NF6: USB_C_GPP_D2] ==> SEN_MODE_EC_PCH_INT_ODL */
+	PAD_CFG_GPI_IRQ_WAKE(GPP_D2, NONE, PLTRST, LEVEL, INVERT),
+	/* D3 : [NF1: ISH_GP3 NF2: BK3 NF5: SBK3 NF6: USB_C_GPP_D3] ==> SOC_TOF_INT# */
+	PAD_CFG_NF(GPP_D3, NONE, DEEP, NF1),
    /* D4  : NC */
    PAD_NC(GPP_D4, NONE),
    /* D5  : NC */
@@ -176,8 +176,8 @@
    PAD_NC(GPP_E7, NONE),
    /* E8  : GPP_E8 ==> WLAN_DISABLE_L */
    PAD_CFG_GPO(GPP_E8, 1, DEEP),
-	/* E9  : NC */
-	PAD_NC_LOCK(GPP_E9, NONE, LOCK_CONFIG),
+	/* E9 : [NF1: USB_OC0# NF2: ISH_GP4 NF6: USB_C_GPP_E9] ==> ISH_MODE_ANGLE_1 */
+	PAD_CFG_NF(GPP_E9, NONE, DEEP, NF2),
    /* E10 : NC */
    PAD_NC_LOCK(GPP_E10, NONE, LOCK_CONFIG),
    /* E11 : NC */