[S] Change in coreboot[main]: mb/purism/librem_l1um_v2/ramstage.c: Use DEV_PTR macro

[Nicholas Chin (Code Review)]

Nicholas Chin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85093?usp=email )

Change subject: mb/purism/librem_l1um_v2/ramstage.c: Use DEV_PTR macro
......................................................................

mb/purism/librem_l1um_v2/ramstage.c: Use DEV_PTR macro

Use the DEV_PTR macro to resolve devicetree aliases instead of using the
autogenerated reference names from sconfig directly.

TEST=Timeless build did not change

Change-Id: I4ff06bb3a8256d5fe215cab659f33ec404264e21
Signed-off-by: Nicholas Chin 
---
M src/mainboard/purism/librem_l1um_v2/ramstage.c
1 file changed, 5 insertions(+), 5 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/85093/1

diff --git a/src/mainboard/purism/librem_l1um_v2/ramstage.c b/src/mainboard/purism/librem_l1um_v2/ramstage.c
index 87b7822..39c078c 100644
--- a/src/mainboard/purism/librem_l1um_v2/ramstage.c
+++ b/src/mainboard/purism/librem_l1um_v2/ramstage.c
@@ -26,13 +26,13 @@
     * Control Register), but we have to use one of the LDNs as the device
     * because the chip ops are only assigned to the LDNs.
     */
-	pnp_enter_conf_mode(_dev_nvt_superio_gpio1_ptr);
+	pnp_enter_conf_mode(DEV_PTR(nvt_superio_gpio1));
    printk(BIOS_DEBUG, "GCR 0x2f was: %02X\n",
-		pnp_read_config(_dev_nvt_superio_gpio1_ptr, 0x2f));
-	pnp_write_config(_dev_nvt_superio_gpio1_ptr, 0x2f, 0x00);
+		pnp_read_config(DEV_PTR(nvt_superio_gpio1), 0x2f));
+	pnp_write_config(DEV_PTR(nvt_superio_gpio1), 0x2f, 0x00);
    printk(BIOS_DEBUG, "GCR 0x2f is now: %02X\n",
-		pnp_read_config(_dev_nvt_superio_gpio1_ptr, 0x2f));
-	pnp_exit_conf_mode(_dev_nvt_superio_gpio1_ptr);
+		pnp_read_config(DEV_PTR(nvt_superio_gpio1), 0x2f));
+	pnp_exit_conf_mode(DEV_PTR(nvt_superio_gpio1));
 }

struct chip_operations mainboard_ops = {