Change in coreboot[master]: soc/intel/skylake: Sideband lock skipped in FSP and done in coreboot

[Barnali Sarkar (Code Review)]

Hello dhaval v sharma, Subrata Banik, Balaji Manigandan, Rizwan Qureshi,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/20956

to look at the new patch set (#4).

Change subject: soc/intel/skylake: Sideband lock skipped in FSP and done in coreboot
......................................................................

soc/intel/skylake: Sideband lock skipped in FSP and done in coreboot

The Sideband Acces locking code is skipped from FSP by setting an
FSP-S UPD called PchSbAccessUnlock This locking is being done in
coreboot during finalize.c.

This is done because Coreboot was failing to disable HECI1 device
using Sideband interface during finalize.c if FSP already locks
the Sideband access mechanism before that.

So, as a solution, coreboot passes an UPD to skip the locking
in FSP, and in finalize.c, after disabling HECI, it removes the
Sideband access.

BUG=b:63877089
BRANCH=none
TEST=Build and boot poppy to check lspci not showing Intel ME
controller in the PCI device list.

Change-Id: I8dba4c97480200507969b0f2873337f97bd2ff6a
Signed-off-by: Barnali Sarkar 
---
M src/soc/intel/skylake/chip_fsp20.c
M src/soc/intel/skylake/finalize.c
2 files changed, 43 insertions(+), 12 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/20956/4