Change in coreboot[master]: mb/intel/shadowmountain: Enable RTD3 for SD card

[Rizwan Qureshi (Code Review)]

Rizwan Qureshi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52134 )

Change subject: mb/intel/shadowmountain: Enable RTD3 for SD card
......................................................................

mb/intel/shadowmountain: Enable RTD3 for SD card

Enable the PCIe RTD3 driver for the PCIe attached SD card interface
and provide the enable/reset GPIOs.

TEST=Tested on shadowmountai platform to ensure the system can enter the
S0i3.2 substate and suspend/resume is stable

Signed-off-by: Rizwan Qureshi 
Change-Id: Ibeb99bea48d72b019cb2adcf38926c3ed39f7b84
---
M src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb
1 file changed, 7 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/52134/1

diff --git a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb
index 8b31784..ffb2065 100644
--- a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb
+++ b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb
@@ -304,7 +304,13 @@
    	device pci 1c.4 on  end # RP5
    	device pci 1c.5 off end # RP6
    	device pci 1c.6 off end # RP7
-		device pci 1c.7 on  end # RP8
+		device pci 1c.7 on
+			chip soc/intel/common/block/pcie/rtd3
+				register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D16)"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H3)"
+				register "srcclk_pin" = "3"
+			end
+		end # RP8
    	device pci 1d.0 on  end # RP9
    	device pci 1d.1 off end # RP10
    	device pci 1d.2 off end # RP11