EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/36524 )
Change subject: mb/google/drallion: Update GPIO table ......................................................................
mb/google/drallion: Update GPIO table
Follow latest GPIO table to change gpio.
BUG=b:143728355 BRANCH=N/A TEST=build pass
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: Iee61c74a5cab5a62a90c0543f212650c4f2420de --- M src/mainboard/google/drallion/variants/drallion/gpio.c 1 file changed, 4 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/36524/1
diff --git a/src/mainboard/google/drallion/variants/drallion/gpio.c b/src/mainboard/google/drallion/variants/drallion/gpio.c index e699e4b..4ad5cfd 100644 --- a/src/mainboard/google/drallion/variants/drallion/gpio.c +++ b/src/mainboard/google/drallion/variants/drallion/gpio.c @@ -39,14 +39,12 @@ /* ESPI_RESET# */ /* SUSACK# */ PAD_CFG_GPO(GPP_A15, 0, DEEP), /* SD_1P8_SEL */ PAD_CFG_GPI(GPP_A16, NONE, PLTRST), /* 2.7MM_CAM_DET# */ -/* SD_PWR_EN# */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF2), - /* ISH_ACC1_INT# */ +/* SD_PWR_EN# */ PAD_NC(GPP_A17, NONE), /* ISH_ACC1_INT# */ /* ISH_GP0 */ PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), /* ISH_ACC2_INT# */ /* ISH_GP1 */ PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), /* ISH_GP2 */ PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1), -/* ISH_GP3 */ PAD_CFG_NF(GPP_A21, NONE, DEEP, NF1), - /* ISH_NB_MODE */ +/* ISH_GP3 */ PAD_NC(GPP_A21, NONE), /* ISH_NB_MODE */ /* ISH_GP4 */ PAD_CFG_NF(GPP_A22, NONE, DEEP, NF1), /* ISH_LID_CL#_NB */ /* ISH_GP5 */ PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1), @@ -64,10 +62,9 @@ /* WLAN_CLKREQ_CPU_N */ /* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* WWAN_CLKREQ_CPU_N */ -/* SRCCLKREQ3# */ PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), - /* SSD_CKLREQ_CPU_N */ +/* SRCCLKREQ3# */ PAD_NC(GPP_B8, NONE), /* SRCCLKREQ4# */ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), -/* SRCCLKREQ5# */ PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), +/* SRCCLKREQ5# */ PAD_NC(GPP_B10, NONE), /* EXT_PWR_GATE# */ PAD_CFG_GPO(GPP_B11, 0, PLTRST), /* 3.3V_CAM_EN# */ /* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* PLTRST# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
John Su has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36524 )
Change subject: mb/google/drallion: Update GPIO table ......................................................................
Patch Set 1: Code-Review+2
Mathew King has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36524 )
Change subject: mb/google/drallion: Update GPIO table ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36524/1/src/mainboard/google/dralli... File src/mainboard/google/drallion/variants/drallion/gpio.c:
https://review.coreboot.org/c/coreboot/+/36524/1/src/mainboard/google/dralli... PS1, Line 47: /* ISH_GP3 */ PAD_NC(GPP_A21, NONE), /* ISH_NB_MODE */ Will this disable the gpio from the ish?
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36524 )
Change subject: mb/google/drallion: Update GPIO table ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36524/1/src/mainboard/google/dralli... File src/mainboard/google/drallion/variants/drallion/gpio.c:
https://review.coreboot.org/c/coreboot/+/36524/1/src/mainboard/google/dralli... PS1, Line 47: /* ISH_GP3 */ PAD_NC(GPP_A21, NONE), /* ISH_NB_MODE */
Will this disable the gpio from the ish?
I think if we set NC, ISH can control this pin. So, yes. @Bora, could you help confirm this?
Bora Guvendik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36524 )
Change subject: mb/google/drallion: Update GPIO table ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36524/1/src/mainboard/google/dralli... File src/mainboard/google/drallion/variants/drallion/gpio.c:
https://review.coreboot.org/c/coreboot/+/36524/1/src/mainboard/google/dralli... PS1, Line 47: /* ISH_GP3 */ PAD_NC(GPP_A21, NONE), /* ISH_NB_MODE */
I think if we set NC, ISH can control this pin. So, yes. […]
Okay according to Tim.
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36524 )
Change subject: mb/google/drallion: Update GPIO table ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36524/1/src/mainboard/google/dralli... File src/mainboard/google/drallion/variants/drallion/gpio.c:
https://review.coreboot.org/c/coreboot/+/36524/1/src/mainboard/google/dralli... PS1, Line 47: /* ISH_GP3 */ PAD_NC(GPP_A21, NONE), /* ISH_NB_MODE */
Okay according to Tim.
I check Arcada... I think I put the wrong comment NB_MODE is A22.. A17 and A21 is NC in Arcada. I fix this later.
Hello Ivy Jian, Mathew King, Bora Guvendik, John Su, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/36524
to look at the new patch set (#2).
Change subject: mb/google/drallion: Update GPIO table ......................................................................
mb/google/drallion: Update GPIO table
Follow latest GPIO table to change gpio.
BUG=b:143728355 BRANCH=N/A TEST=build pass
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: Iee61c74a5cab5a62a90c0543f212650c4f2420de --- M src/mainboard/google/drallion/variants/drallion/gpio.c 1 file changed, 4 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/36524/2
Hello Ivy Jian, Mathew King, Bora Guvendik, John Su, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/36524
to look at the new patch set (#3).
Change subject: mb/google/drallion: Update GPIO table ......................................................................
mb/google/drallion: Update GPIO table
Follow latest GPIO table to change gpio.
BUG=b:143728355 BRANCH=N/A TEST=build pass
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: Iee61c74a5cab5a62a90c0543f212650c4f2420de --- M src/mainboard/google/drallion/variants/drallion/gpio.c 1 file changed, 4 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/36524/3
Mathew King has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36524 )
Change subject: mb/google/drallion: Update GPIO table ......................................................................
Patch Set 3: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/36524 )
Change subject: mb/google/drallion: Update GPIO table ......................................................................
mb/google/drallion: Update GPIO table
Follow latest GPIO table to change gpio.
BUG=b:143728355 BRANCH=N/A TEST=build pass
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: Iee61c74a5cab5a62a90c0543f212650c4f2420de Reviewed-on: https://review.coreboot.org/c/coreboot/+/36524 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Mathew King mathewk@chromium.org --- M src/mainboard/google/drallion/variants/drallion/gpio.c 1 file changed, 4 insertions(+), 5 deletions(-)
Approvals: build bot (Jenkins): Verified Mathew King: Looks good to me, approved
diff --git a/src/mainboard/google/drallion/variants/drallion/gpio.c b/src/mainboard/google/drallion/variants/drallion/gpio.c index 697d305..5657eea 100644 --- a/src/mainboard/google/drallion/variants/drallion/gpio.c +++ b/src/mainboard/google/drallion/variants/drallion/gpio.c @@ -39,13 +39,13 @@ /* ESPI_RESET# */ /* SUSACK# */ PAD_CFG_GPO(GPP_A15, 0, DEEP), /* SD_1P8_SEL */ PAD_CFG_GPI(GPP_A16, NONE, PLTRST), /* 2.7MM_CAM_DET# */ -/* SD_PWR_EN# */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF2), +/* SD_PWR_EN# */ PAD_NC(GPP_A17, NONE), /* ISH_ACC1_INT# */ /* ISH_GP0 */ PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), /* ISH_ACC2_INT# */ /* ISH_GP1 */ PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), /* ISH_GP2 */ PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1), -/* ISH_GP3 */ PAD_CFG_NF(GPP_A21, NONE, DEEP, NF1), +/* ISH_GP3 */ PAD_NC(GPP_A21, NONE), /* ISH_NB_MODE */ /* ISH_GP4 */ PAD_CFG_NF(GPP_A22, NONE, DEEP, NF1), /* ISH_LID_CL#_NB */ @@ -63,11 +63,10 @@ /* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* WLAN_CLKREQ_CPU_N */ /* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), - /* WWAN_CLKREQ_CPU_N */ -/* SRCCLKREQ3# */ PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), +/* SRCCLKREQ3# */ PAD_NC(GPP_B8, NONE), /* SSD_CKLREQ_CPU_N */ /* SRCCLKREQ4# */ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), -/* SRCCLKREQ5# */ PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), +/* SRCCLKREQ5# */ PAD_NC(GPP_B10, NONE), /* EXT_PWR_GATE# */ PAD_CFG_GPO(GPP_B11, 0, PLTRST), /* 3.3V_CAM_EN# */ /* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* PLTRST# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),