Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/28769 )
Change subject: amd/stoneyridge: Add ASL for D-states on AOAC devices ......................................................................
Patch Set 1:
(2 comments)
https://review.coreboot.org/#/c/28769/1/src/soc/amd/stoneyridge/acpi/sb_pci0... File src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl:
https://review.coreboot.org/#/c/28769/1/src/soc/amd/stoneyridge/acpi/sb_pci0... PS1, Line 444: Case(Package() {5, 15, 24}) { : Store(One, PG1A) : } : Case(Package() {6, 7, 8, 11, 12, 18}) { : Store(One, PG2_) : } :
What about Arg0 = 23?
These are power groups. xHCI is on its own power, as I read it (AOACxA0[3]). This also mirrors AMD's code.
https://review.coreboot.org/#/c/28769/1/src/soc/amd/stoneyridge/acpi/sb_pci0... PS1, Line 557: * todo Case(15) { STD3()} */ /* SATA *
default?
I'd prefer to keep it as close to AMD's code as possible. I'll add a default if static analysis suggests it, but basically I want there to be no default behavior.
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Marshall Dawson (Code Review)