[S] Change in coreboot[main]: sb/intel/bd82x6x: assign PCH HDA controller ops in chipset devicetree

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79118?usp=email )

(

1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
 )Change subject: sb/intel/bd82x6x: assign PCH HDA controller ops in chipset devicetree
......................................................................

sb/intel/bd82x6x: assign PCH HDA controller ops in chipset devicetree

Since the HD audio controller in the PCH are always on the same device
functions, the device operations can be statically assigned in the
devicetree and there's no need to bind the host bridge device operations
to the PCI device during runtime via a list of PCI IDs.

TEST=Lenovo X220 still boots to Linux and audio still works

Signed-off-by: Felix Held 
Tested-by: Patrick Rudolph 
Change-Id: I9bbbe9f4490dc6fb21174d63d1c8906d69ea3ee0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79118
Reviewed-by: Patrick Rudolph 
Tested-by: build bot (Jenkins) 
---
M src/northbridge/intel/sandybridge/chipset.cb
M src/southbridge/intel/bd82x6x/azalia.c
2 files changed, 2 insertions(+), 10 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Patrick Rudolph: Looks good to me, approved

diff --git a/src/northbridge/intel/sandybridge/chipset.cb b/src/northbridge/intel/sandybridge/chipset.cb
index c3c35c1..a08b1bd 100644
--- a/src/northbridge/intel/sandybridge/chipset.cb
+++ b/src/northbridge/intel/sandybridge/chipset.cb
@@ -26,7 +26,7 @@
    		device pci 16.3 alias me_kt off end      # Management Engine KT
    		device pci 19.0 alias gbe off end        # Intel Gigabit Ethernet
    		device pci 1a.0 alias ehci2 off end      # USB2 EHCI #2
-			device pci 1b.0 alias hda off end        # High Definition Audio
+			device pci 1b.0 alias hda off ops bd82x6x_azalia_ops end        # High Definition Audio
    		device pci 1c.0 alias pcie_rp1 off ops bd82x6x_pcie_rp_ops end   # PCIe Port #1
    		device pci 1c.1 alias pcie_rp2 off ops bd82x6x_pcie_rp_ops end   # PCIe Port #2
    		device pci 1c.2 alias pcie_rp3 off ops bd82x6x_pcie_rp_ops end   # PCIe Port #3
diff --git a/src/southbridge/intel/bd82x6x/azalia.c b/src/southbridge/intel/bd82x6x/azalia.c
index 97884c6..ddaa8a1 100644
--- a/src/southbridge/intel/bd82x6x/azalia.c
+++ b/src/southbridge/intel/bd82x6x/azalia.c
@@ -122,7 +122,7 @@
    return "HDEF";
 }

-static struct device_operations azalia_ops = {
+struct device_operations bd82x6x_azalia_ops = {
    .read_resources		= pci_dev_read_resources,
    .set_resources		= pci_dev_set_resources,
    .enable_resources	= pci_dev_enable_resources,
@@ -130,11 +130,3 @@
    .ops_pci		= &pci_dev_ops_pci,
    .acpi_name		= azalia_acpi_name,
 };
-
-static const unsigned short pci_device_ids[] = { 0x1c20, 0x1e20, 0 };
-
-static const struct pci_driver pch_azalia __pci_driver = {
-	.ops	 = &azalia_ops,
-	.vendor	 = PCI_VID_INTEL,
-	.devices = pci_device_ids,
-};