Attention is currently required from: Angel Pons, Keith Hui, Nicholas Chin.
Bill XIE has posted comments on this change by Keith Hui. ( https://review.coreboot.org/c/coreboot/+/85413?usp=email )
Change subject: mb/asus/p8z77-v: Attempt to correctly route PCIe lanes ......................................................................
Patch Set 7:
(1 comment)
File src/mainboard/asus/p8x7x-series/variants/p8z77-v/early_init.c:
https://review.coreboot.org/c/coreboot/+/85413/comment/3bfa8ee4_6bfd4c8e?usp... : PS7, Line 104: 0x40 Let Setup = /sys/firmware/efi/efivars/Setup-ec87d643-eba4-4bb5-a1e5-3f3e36b20da9 , my result is:
PCIEX1_2: Setup[0x820] == 0, Setup[0x824] == 2; ASM1061: Setup[0x820] == 0, Setup[0x824] == 0; x4: Setup[0x820] == 0, Setup[0x824] == 1;
Besides, on patchset 7, when (force_asm1061 == false), if a card is present on PCIEX1_2 X_QSW_SEL2,3,4 is 111, and if not present, X_QSW_SEL2,3,4 is correctly 110.
If a descriptor with (PCIEPCS1 == 1) is flashed with patchset 7, PCIEX16_3 can be confirmed working with x2, with on-board ASM1061 working with X_QSW_SEL2,3,4 being 010. PCIEX1_2 remains not working in this mode, with X_QSW_SEL2,3,4 being 011 and the following log:
[DEBUG] PCI: 00:00:1c.3 scanning...
[DEBUG] PCI: pci_scan_bus for segment group 00 bus 06 [INFO ] POST: 0x24 [INFO ] POST: 0x25 [INFO ] PCI: 00:00:1c.3: Setting Max_Payload_Size to 128 for devices under this root port [WARN ] PCI: 00:00:1c.3: Has a slow downstream device. Enumeration failed. [DEBUG] scan_bus: bus PCI: 00:00:1c.3 finished in 26 msecs
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Bill XIE (Code Review)