[XL] Change in coreboot[main]: soc/mediatek/mt8196: Add eDP driver

[Bincai Liu (Code Review)]

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yidi Lin, Yu-Ping Wu.

Bincai Liu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85949?usp=email )

Change subject: soc/mediatek/mt8196: Add eDP driver
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Patch Set 4:

(16 comments)

File src/soc/mediatek/mt8196/dp_intf.c:

https://review.coreboot.org/c/coreboot/+/85949/comment/b6df42c0_740b6feb?usp... :
PS2, Line 12: static struct mtk_dvo_gs_info mtk_dvo_gs[MTK_DVO_GSL_MAX] = {
> done

Done

https://review.coreboot.org/c/coreboot/+/85949/comment/18bb6aa3_8d09b836?usp... :
PS2, Line 18: {
> it seems that we do not need to check whether all bits of val are also set in mask.

Done

https://review.coreboot.org/c/coreboot/+/85949/comment/665db7b9_09ba4348?usp... :
PS2, Line 32: struct
> done

Done

https://review.coreboot.org/c/coreboot/+/85949/comment/0f8380ca_dc09f380?usp... :
PS2, Line 34: HFP_MASK
> done

Done

https://review.coreboot.org/c/coreboot/+/85949/comment/eab4ecc1_626b9c46?usp... :
PS2, Line 35: HFP_MASK << HFP
> done

Done

https://review.coreboot.org/c/coreboot/+/85949/comment/0187b50d_bc1d9217?usp... :
PS2, Line 40: struct
> done

Done

https://review.coreboot.org/c/coreboot/+/85949/comment/3528a534_11ec0a05?usp... :
PS2, Line 62: PIC_HSIZE_MASK << SRC_HSIZE
> i fixed it, please help to check it again, thanks a lot

Done

https://review.coreboot.org/c/coreboot/+/85949/comment/e9b9b866_99b3ec3f?usp... :
PS2, Line 102: MTK_DVO_8K_30FPS
> gs_level is for different kind of resolutions for register DVO_BUF_SODI_HIGHT and DVO_BUF_SODI_LOW

Done

https://review.coreboot.org/c/coreboot/+/85949/comment/641de06c_107e8870?usp... :
PS2, Line 160:
> yes

Done

https://review.coreboot.org/c/coreboot/+/85949/comment/9131d06f_062b1bab?usp... :
PS2, Line 198: mtk_dvo_power_on
> the function of mtk_dpintf_power_on and mtk_dvo_power_on is same

Done

File src/soc/mediatek/mt8196/dptx.c:

https://review.coreboot.org/c/coreboot/+/85949/comment/0f8f22e6_77028724?usp... :
PS2, Line 276: 	case DP_LINKRATE_HBR2:
> yes

Done

https://review.coreboot.org/c/coreboot/+/85949/comment/9595f458_370a547b?usp... :
PS2, Line 369: 	printk(BIOS_INFO, "[eDPTX] begin\n");
> yes

Done

https://review.coreboot.org/c/coreboot/+/85949/comment/1875805e_be2c7141?usp... :
PS2, Line 372: write32p(MMSYS1_CONFIG_BASE + MMSYS1_CG_CLR0, 0xFFFFFFFF);
             : 	write32p(MMSYS1_CONFIG_BASE + MMSYS1_CG_CLR1, 0x00040000);
> this register is to select clock source for edp mac and dvo

Done

https://review.coreboot.org/c/coreboot/+/85949/comment/8f8ae4a2_d3a6d167?usp... :
PS2, Line 374: m
> yes

Done

https://review.coreboot.org/c/coreboot/+/85949/comment/29472d7b_c488c190?usp... :
PS2, Line 375: 0xff000000
> this register is to enable select clock source for eDP

Done

File src/soc/mediatek/mt8196/dptx_hal.c:

https://review.coreboot.org/c/coreboot/+/85949/comment/1002d002_676b3d63?usp... :
PS2, Line 307: mtk_edp_hal_reset_swing_pre_emphasis
> registers in mtk_edp_hal_reset_swing_pre_emphasis and dptx_hal_reset_swing_preemphasis are different […]

Done