Change in coreboot[master]: soc/intel/skylake: Enable SDXC depending on devicetree configuration

[Felix Singer (Code Review)]

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44028 )

Change subject: soc/intel/skylake: Enable SDXC depending on devicetree configuration
......................................................................

soc/intel/skylake: Enable SDXC depending on devicetree configuration

Currently SDXC gets enabled by the option ScsSdCardEnabled,
but this duplicates the devicetree on/off options. Therefore use the
on/off options for the enablement of the SDXC controller.

I checked all corresponding mainboards if the devicetree configuration
matches the ScsSdCardEnabled setting.

Change-Id: I298b7d0b0fe2a7346dbadcea4be22dc67fce4de8
Signed-off-by: Felix Singer 
---
M src/soc/intel/skylake/chip.c
M src/soc/intel/skylake/chip.h
2 files changed, 3 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/44028/1

diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c
index 6423cf4..cb0d2fc 100644
--- a/src/soc/intel/skylake/chip.c
+++ b/src/soc/intel/skylake/chip.c
@@ -257,7 +257,9 @@
    dev = pcidev_path_on_root(PCH_DEVFN_EMMC);
    params->ScsEmmcEnabled = dev ? dev->enabled : 0;
    params->ScsEmmcHs400Enabled = config->ScsEmmcHs400Enabled;
-	params->ScsSdCardEnabled = config->ScsSdCardEnabled;
+
+	dev = pcidev_path_on_root(PCH_DEVFN_SDCARD);
+	params->ScsSdCardEnabled = dev && dev->enabled;

if (!!params->ScsEmmcHs400Enabled && !!config->EmmcHs400DllNeed) {
    	params->PchScsEmmcHs400DllDataValid =
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h
index e332a6b..404a9f4 100644
--- a/src/soc/intel/skylake/chip.h
+++ b/src/soc/intel/skylake/chip.h
@@ -306,7 +306,6 @@

/* eMMC and SD */
    u8 ScsEmmcHs400Enabled;
-	u8 ScsSdCardEnabled;
    u8 EmmcHs400DllNeed;
    u8 ScsEmmcHs400RxStrobeDll1;
    u8 ScsEmmcHs400TxDataDll;

[Felix Singer (Code Review)]

Hello build bot (Jenkins), Paul Menzel, Michael Niewöhner, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/44028

to look at the new patch set (#2).

Change subject: soc/intel/skylake: Enable SDXC depending on devicetree configuration
......................................................................

soc/intel/skylake: Enable SDXC depending on devicetree configuration

Currently SDXC gets enabled by the option ScsSdCardEnabled,
but this duplicates the devicetree on/off options. Therefore use the
on/off options for the enablement of the SDXC controller.

I checked all corresponding mainboards if the devicetree configuration
matches the ScsSdCardEnabled setting.

Change-Id: I298b7d0b0fe2a7346dbadcea4be22dc67fce4de8
Signed-off-by: Felix Singer 
---
M src/mainboard/51nb/x210/devicetree.cb
M src/mainboard/asrock/h110m/devicetree.cb
M src/mainboard/google/eve/devicetree.cb
M src/mainboard/google/fizz/variants/baseboard/devicetree.cb
M src/mainboard/google/glados/devicetree.cb
M src/mainboard/google/glados/variants/caroline/overridetree.cb
M src/mainboard/google/glados/variants/cave/overridetree.cb
M src/mainboard/google/glados/variants/glados/overridetree.cb
M src/mainboard/google/glados/variants/sentry/overridetree.cb
M src/mainboard/google/poppy/variants/atlas/devicetree.cb
M src/mainboard/google/poppy/variants/baseboard/devicetree.cb
M src/mainboard/google/poppy/variants/nami/devicetree.cb
M src/mainboard/google/poppy/variants/nautilus/devicetree.cb
M src/mainboard/google/poppy/variants/nocturne/devicetree.cb
M src/mainboard/google/poppy/variants/rammus/devicetree.cb
M src/mainboard/google/poppy/variants/soraka/devicetree.cb
M src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb
M src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb
M src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb
M src/mainboard/intel/kunimitsu/devicetree.cb
M src/mainboard/intel/saddlebrook/devicetree.cb
M src/mainboard/libretrend/lt1000/devicetree.cb
M src/mainboard/protectli/vault_kbl/devicetree.cb
M src/mainboard/purism/librem_skl/devicetree.cb
M src/mainboard/razer/blade_stealth_kbl/devicetree.cb
M src/mainboard/supermicro/x11-lga1151-series/devicetree.cb
M src/soc/intel/skylake/chip.c
M src/soc/intel/skylake/chip.h
28 files changed, 9 insertions(+), 32 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/44028/2

[Michael Niewöhner (Code Review)]

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44028 )

Change subject: soc/intel/skylake: Enable SDXC depending on devicetree configuration
......................................................................

Patch Set 2:

(2 comments)

https://review.coreboot.org/c/coreboot/+/44028/2//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/44028/2//COMMIT_MSG@10 
PS2, Line 10: but this duplicates the devicetree on/off options. Therefore use the
            : on/off options for the enablement of the SDXC controller.
            : 
... depend on the devicetree for enablement ...

https://review.coreboot.org/c/coreboot/+/44028/2//COMMIT_MSG@14 
PS2, Line 14: matches the ScsSdCardEnabled setting.
and addded missing entries

[Felix Singer (Code Review)]

Hello build bot (Jenkins), Michał Żygowski, Paul Menzel, Michael Niewöhner, Patrick Rudolph, Piotr Król,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/44028

to look at the new patch set (#3).

Change subject: soc/intel/skylake: Enable SDXC depending on devicetree configuration
......................................................................

soc/intel/skylake: Enable SDXC depending on devicetree configuration

Currently, SDXC gets enabled by the option ScsSdCardEnabled,
but this duplicates the devicetree on/off options. Therefore, depend on
the devicetree for the enablement of the SDXC controller.

All corresponding mainboards were checked if the devicetree
configuration matches the ScsSdCardEnabled setting, and missing
entries were added.

Change-Id: I298b7d0b0fe2a7346dbadcea4be22dc67fce4de8
Signed-off-by: Felix Singer 
---
M src/mainboard/51nb/x210/devicetree.cb
M src/mainboard/asrock/h110m/devicetree.cb
M src/mainboard/google/eve/devicetree.cb
M src/mainboard/google/fizz/variants/baseboard/devicetree.cb
M src/mainboard/google/glados/devicetree.cb
M src/mainboard/google/glados/variants/caroline/overridetree.cb
M src/mainboard/google/glados/variants/cave/overridetree.cb
M src/mainboard/google/glados/variants/glados/overridetree.cb
M src/mainboard/google/glados/variants/sentry/overridetree.cb
M src/mainboard/google/poppy/variants/atlas/devicetree.cb
M src/mainboard/google/poppy/variants/baseboard/devicetree.cb
M src/mainboard/google/poppy/variants/nami/devicetree.cb
M src/mainboard/google/poppy/variants/nautilus/devicetree.cb
M src/mainboard/google/poppy/variants/nocturne/devicetree.cb
M src/mainboard/google/poppy/variants/rammus/devicetree.cb
M src/mainboard/google/poppy/variants/soraka/devicetree.cb
M src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb
M src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb
M src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb
M src/mainboard/intel/kunimitsu/devicetree.cb
M src/mainboard/intel/saddlebrook/devicetree.cb
M src/mainboard/libretrend/lt1000/devicetree.cb
M src/mainboard/protectli/vault_kbl/devicetree.cb
M src/mainboard/purism/librem_skl/devicetree.cb
M src/mainboard/razer/blade_stealth_kbl/devicetree.cb
M src/mainboard/supermicro/x11-lga1151-series/devicetree.cb
M src/soc/intel/skylake/chip.c
M src/soc/intel/skylake/chip.h
28 files changed, 9 insertions(+), 32 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/44028/3

[Felix Singer (Code Review)]

Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44028 )

Change subject: soc/intel/skylake: Enable SDXC depending on devicetree configuration
......................................................................

Patch Set 3:

(2 comments)

https://review.coreboot.org/c/coreboot/+/44028/2//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/44028/2//COMMIT_MSG@10 
PS2, Line 10: but this duplicates the devicetree on/off options. Therefore use the
            : on/off options for the enablement of the SDXC controller.
            :
> ... depend on the devicetree for enablement ...

Done

https://review.coreboot.org/c/coreboot/+/44028/2//COMMIT_MSG@14 
PS2, Line 14: matches the ScsSdCardEnabled setting.
> and addded missing entries

Done

[Michael Niewöhner (Code Review)]

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44028 )

Change subject: soc/intel/skylake: Enable SDXC depending on devicetree configuration
......................................................................

Patch Set 3: Code-Review+2

[Felix Singer (Code Review)]

Hello build bot (Jenkins), Michał Żygowski, Paul Menzel, Michael Niewöhner, Patrick Rudolph, Piotr Król,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/44028

to look at the new patch set (#4).

Change subject: soc/intel/skylake: Enable SDXC depending on devicetree configuration
......................................................................

soc/intel/skylake: Enable SDXC depending on devicetree configuration

Currently, SDXC gets enabled by the option ScsSdCardEnabled,
but this duplicates the devicetree on/off options. Therefore, depend on
the devicetree for the enablement of the SDXC controller.

All corresponding mainboards were checked if the devicetree
configuration matches the ScsSdCardEnabled setting, and missing
entries were added.

Change-Id: I298b7d0b0fe2a7346dbadcea4be22dc67fce4de8
Signed-off-by: Felix Singer 
---
M src/mainboard/51nb/x210/devicetree.cb
M src/mainboard/google/eve/devicetree.cb
M src/mainboard/google/fizz/variants/baseboard/devicetree.cb
M src/mainboard/google/glados/devicetree.cb
M src/mainboard/google/glados/variants/caroline/overridetree.cb
M src/mainboard/google/glados/variants/cave/overridetree.cb
M src/mainboard/google/glados/variants/glados/overridetree.cb
M src/mainboard/google/glados/variants/sentry/overridetree.cb
M src/mainboard/google/poppy/variants/atlas/devicetree.cb
M src/mainboard/google/poppy/variants/baseboard/devicetree.cb
M src/mainboard/google/poppy/variants/nami/devicetree.cb
M src/mainboard/google/poppy/variants/nautilus/devicetree.cb
M src/mainboard/google/poppy/variants/nocturne/devicetree.cb
M src/mainboard/google/poppy/variants/rammus/devicetree.cb
M src/mainboard/google/poppy/variants/soraka/devicetree.cb
M src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb
M src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb
M src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb
M src/mainboard/intel/kunimitsu/devicetree.cb
M src/mainboard/intel/saddlebrook/devicetree.cb
M src/mainboard/libretrend/lt1000/devicetree.cb
M src/mainboard/protectli/vault_kbl/devicetree.cb
M src/mainboard/purism/librem_skl/devicetree.cb
M src/mainboard/razer/blade_stealth_kbl/devicetree.cb
M src/mainboard/supermicro/x11-lga1151-series/devicetree.cb
M src/soc/intel/skylake/chip.c
M src/soc/intel/skylake/chip.h
27 files changed, 9 insertions(+), 31 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/44028/4

[Felix Singer (Code Review)]

Hello build bot (Jenkins), Michał Żygowski, Paul Menzel, Michael Niewöhner, Patrick Rudolph, Piotr Król,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/44028

to look at the new patch set (#5).

Change subject: soc/intel/skylake: Enable SDXC depending on devicetree configuration
......................................................................

soc/intel/skylake: Enable SDXC depending on devicetree configuration

Currently, SDXC gets enabled by the option ScsSdCardEnabled,
but this duplicates the devicetree on/off options. Therefore, depend on
the devicetree for the enablement of the SDXC controller.

All corresponding mainboards were checked if the devicetree
configuration matches the ScsSdCardEnabled setting, and missing
entries were added.

Change-Id: I298b7d0b0fe2a7346dbadcea4be22dc67fce4de8
Signed-off-by: Felix Singer 
---
M src/mainboard/51nb/x210/devicetree.cb
M src/mainboard/asrock/h110m/devicetree.cb
M src/mainboard/google/eve/devicetree.cb
M src/mainboard/google/fizz/variants/baseboard/devicetree.cb
M src/mainboard/google/glados/devicetree.cb
M src/mainboard/google/glados/variants/caroline/overridetree.cb
M src/mainboard/google/glados/variants/cave/overridetree.cb
M src/mainboard/google/glados/variants/glados/overridetree.cb
M src/mainboard/google/glados/variants/sentry/overridetree.cb
M src/mainboard/google/poppy/variants/atlas/devicetree.cb
M src/mainboard/google/poppy/variants/baseboard/devicetree.cb
M src/mainboard/google/poppy/variants/nami/devicetree.cb
M src/mainboard/google/poppy/variants/nautilus/devicetree.cb
M src/mainboard/google/poppy/variants/nocturne/devicetree.cb
M src/mainboard/google/poppy/variants/rammus/devicetree.cb
M src/mainboard/google/poppy/variants/soraka/devicetree.cb
M src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb
M src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb
M src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb
M src/mainboard/intel/kunimitsu/devicetree.cb
M src/mainboard/intel/saddlebrook/devicetree.cb
M src/mainboard/libretrend/lt1000/devicetree.cb
M src/mainboard/protectli/vault_kbl/devicetree.cb
M src/mainboard/purism/librem_skl/devicetree.cb
M src/mainboard/razer/blade_stealth_kbl/devicetree.cb
M src/mainboard/supermicro/x11-lga1151-series/devicetree.cb
M src/soc/intel/skylake/chip.c
M src/soc/intel/skylake/chip.h
28 files changed, 10 insertions(+), 34 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/44028/5

[Michael Niewöhner (Code Review)]

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44028 )

Change subject: soc/intel/skylake: Enable SDXC depending on devicetree configuration
......................................................................

Patch Set 5: Code-Review+2

[Michael Niewöhner (Code Review)]

Michael Niewöhner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/44028 )

Change subject: soc/intel/skylake: Enable SDXC depending on devicetree configuration
......................................................................

soc/intel/skylake: Enable SDXC depending on devicetree configuration

Currently, SDXC gets enabled by the option ScsSdCardEnabled,
but this duplicates the devicetree on/off options. Therefore, depend on
the devicetree for the enablement of the SDXC controller.

All corresponding mainboards were checked if the devicetree
configuration matches the ScsSdCardEnabled setting, and missing
entries were added.

Change-Id: I298b7d0b0fe2a7346dbadcea4be22dc67fce4de8
Signed-off-by: Felix Singer 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44028
Tested-by: build bot (Jenkins) 
Reviewed-by: Michael Niewöhner
---
M src/mainboard/51nb/x210/devicetree.cb
M src/mainboard/asrock/h110m/devicetree.cb
M src/mainboard/google/eve/devicetree.cb
M src/mainboard/google/fizz/variants/baseboard/devicetree.cb
M src/mainboard/google/glados/devicetree.cb
M src/mainboard/google/glados/variants/caroline/overridetree.cb
M src/mainboard/google/glados/variants/cave/overridetree.cb
M src/mainboard/google/glados/variants/glados/overridetree.cb
M src/mainboard/google/glados/variants/sentry/overridetree.cb
M src/mainboard/google/poppy/variants/atlas/devicetree.cb
M src/mainboard/google/poppy/variants/baseboard/devicetree.cb
M src/mainboard/google/poppy/variants/nami/devicetree.cb
M src/mainboard/google/poppy/variants/nautilus/devicetree.cb
M src/mainboard/google/poppy/variants/nocturne/devicetree.cb
M src/mainboard/google/poppy/variants/rammus/devicetree.cb
M src/mainboard/google/poppy/variants/soraka/devicetree.cb
M src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb
M src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb
M src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb
M src/mainboard/intel/kunimitsu/devicetree.cb
M src/mainboard/intel/saddlebrook/devicetree.cb
M src/mainboard/libretrend/lt1000/devicetree.cb
M src/mainboard/protectli/vault_kbl/devicetree.cb
M src/mainboard/purism/librem_skl/devicetree.cb
M src/mainboard/razer/blade_stealth_kbl/devicetree.cb
M src/mainboard/supermicro/x11-lga1151-series/devicetree.cb
M src/soc/intel/skylake/chip.c
M src/soc/intel/skylake/chip.h
28 files changed, 10 insertions(+), 34 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Michael Niewöhner: Looks good to me, approved

diff --git a/src/mainboard/51nb/x210/devicetree.cb b/src/mainboard/51nb/x210/devicetree.cb
index d6ad862..b3d9929 100644
--- a/src/mainboard/51nb/x210/devicetree.cb
+++ b/src/mainboard/51nb/x210/devicetree.cb
@@ -51,7 +51,6 @@
    register "SsicPortEnable" = "0"
    register "Cio2Enable" = "0"
    register "ScsEmmcHs400Enabled" = "0"
-	register "ScsSdCardEnabled" = "0"
    register "PttSwitch" = "0"
    register "SkipExtGfxScan" = "1"
    register "HeciEnabled" = "1"
@@ -144,6 +143,7 @@
    	device pci 1d.1 off end # PCI Express Port 10
    	device pci 1d.2 off end # PCI Express Port 11
    	device pci 1d.3 off end # PCI Express Port 12
+		device pci 1e.6 off end # SDXC
    	device pci 1f.0 on
    		chip ec/51nb/npce985la0dx
    			device pnp 0c09.0 on end
diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb
index 6de2a63..d6f29a2 100644
--- a/src/mainboard/asrock/h110m/devicetree.cb
+++ b/src/mainboard/asrock/h110m/devicetree.cb
@@ -265,9 +265,7 @@
    	device pci 1e.3 off end # GSPI #1
    	device pci 1e.4 off end # eMMC
    	device pci 1e.5 off end # SDIO
-		device pci 1e.6 off     # SDCard
-			register "ScsSdCardEnabled" = "0"
-		end
+		device pci 1e.6 off end # SDCard
    	device pci 1f.0 on      # LPC bridge
    		subsystemid 0x1849 0x1a43

diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb
index 8a459f7..8d15e8e 100644
--- a/src/mainboard/google/eve/devicetree.cb
+++ b/src/mainboard/google/eve/devicetree.cb
@@ -44,7 +44,6 @@
    register "SsicPortEnable" = "0"
    register "Cio2Enable" = "0"
    register "ScsEmmcHs400Enabled" = "1"
-	register "ScsSdCardEnabled" = "0"
    register "PttSwitch" = "0"
    register "SkipExtGfxScan" = "1"
    register "HeciEnabled" = "0"
diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb
index 651f174..e8412d5 100644
--- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb
@@ -75,7 +75,6 @@
    register "SsicPortEnable" = "0"
    register "Cio2Enable" = "0"
    register "ScsEmmcHs400Enabled" = "0"
-	register "ScsSdCardEnabled" = "2"
    register "PttSwitch" = "0"
    register "SkipExtGfxScan" = "1"
    register "HeciEnabled" = "0"
diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb
index f2d7c64..108470b 100644
--- a/src/mainboard/google/glados/devicetree.cb
+++ b/src/mainboard/google/glados/devicetree.cb
@@ -46,7 +46,6 @@
    register "SsicPortEnable" = "0"
    register "Cio2Enable" = "0"
    register "ScsEmmcHs400Enabled" = "1"
-	register "ScsSdCardEnabled" = "0"
    register "PttSwitch" = "0"
    register "SkipExtGfxScan" = "1"
    register "HeciEnabled" = "0"
diff --git a/src/mainboard/google/glados/variants/caroline/overridetree.cb b/src/mainboard/google/glados/variants/caroline/overridetree.cb
index 7bee2e2..b1f3e8b 100644
--- a/src/mainboard/google/glados/variants/caroline/overridetree.cb
+++ b/src/mainboard/google/glados/variants/caroline/overridetree.cb
@@ -1,7 +1,5 @@
 chip soc/intel/skylake

-	register "ScsSdCardEnabled" = "2"
-
    register "PmConfigSlpS4MinAssert" = "1"		# 1s
    register "PmConfigSlpSusMinAssert" = "1"	# 500ms

diff --git a/src/mainboard/google/glados/variants/cave/overridetree.cb b/src/mainboard/google/glados/variants/cave/overridetree.cb
index 9aeb78a..7753dd4 100644
--- a/src/mainboard/google/glados/variants/cave/overridetree.cb
+++ b/src/mainboard/google/glados/variants/cave/overridetree.cb
@@ -1,7 +1,5 @@
 chip soc/intel/skylake

-	register "ScsSdCardEnabled" = "2"
-
    register "PmConfigSlpS4MinAssert" = "1"		# 1s
    register "PmConfigSlpSusMinAssert" = "1"	# 500ms

diff --git a/src/mainboard/google/glados/variants/glados/overridetree.cb b/src/mainboard/google/glados/variants/glados/overridetree.cb
index c510e92..3a0fdd4 100644
--- a/src/mainboard/google/glados/variants/glados/overridetree.cb
+++ b/src/mainboard/google/glados/variants/glados/overridetree.cb
@@ -1,7 +1,5 @@
 chip soc/intel/skylake

-	register "ScsSdCardEnabled" = "2"
-
    register "PmConfigSlpS4MinAssert" = "1"		# 1s
    register "PmConfigSlpSusMinAssert" = "1"	# 500ms

diff --git a/src/mainboard/google/glados/variants/sentry/overridetree.cb b/src/mainboard/google/glados/variants/sentry/overridetree.cb
index 08d3dd3..36575f8 100644
--- a/src/mainboard/google/glados/variants/sentry/overridetree.cb
+++ b/src/mainboard/google/glados/variants/sentry/overridetree.cb
@@ -1,7 +1,5 @@
 chip soc/intel/skylake

-	register "ScsSdCardEnabled" = "2"
-
    register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)"	# Type-C Port 1
    register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC1)"	# Type-C Port 2
    register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)"	# Bluetooth
diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb
index eae9835..73f8281 100644
--- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb
@@ -51,7 +51,6 @@
    register "Cio2Enable" = "1"
    register "SaImguEnable" = "1"
    register "ScsEmmcHs400Enabled" = "1"
-	register "ScsSdCardEnabled" = "0"
    register "PttSwitch" = "0"
    register "SkipExtGfxScan" = "1"
    register "HeciEnabled" = "0"
diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb
index ea6267f..8c638ba 100644
--- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb
@@ -41,7 +41,6 @@
    register "Cio2Enable" = "1"
    register "SaImguEnable" = "1"
    register "ScsEmmcHs400Enabled" = "1"
-	register "ScsSdCardEnabled" = "2"
    register "PttSwitch" = "0"
    register "SkipExtGfxScan" = "1"
    register "HeciEnabled" = "0"
diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb
index 98568f8..851e240 100644
--- a/src/mainboard/google/poppy/variants/nami/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb
@@ -40,7 +40,6 @@
    register "Cio2Enable" = "0"
    register "SaImguEnable" = "0"
    register "ScsEmmcHs400Enabled" = "1"
-	register "ScsSdCardEnabled" = "0"
    register "PttSwitch" = "0"
    register "SkipExtGfxScan" = "1"
    register "HeciEnabled" = "0"
diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb
index 43d6509..e4f3112 100644
--- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb
@@ -41,7 +41,6 @@
    register "Cio2Enable" = "1"
    register "SaImguEnable" = "1"
    register "ScsEmmcHs400Enabled" = "1"
-	register "ScsSdCardEnabled" = "2"
    register "PttSwitch" = "0"
    register "SkipExtGfxScan" = "1"
    register "HeciEnabled" = "0"
diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb
index 2bd82a9..c7540e9 100644
--- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb
@@ -46,7 +46,6 @@
    register "Cio2Enable" = "1"
    register "SaImguEnable" = "1"
    register "ScsEmmcHs400Enabled" = "1"
-	register "ScsSdCardEnabled" = "0"
    register "PttSwitch" = "0"
    register "SkipExtGfxScan" = "1"
    register "HeciEnabled" = "0"
diff --git a/src/mainboard/google/poppy/variants/rammus/devicetree.cb b/src/mainboard/google/poppy/variants/rammus/devicetree.cb
index ef5cd1b..0c221af 100644
--- a/src/mainboard/google/poppy/variants/rammus/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/rammus/devicetree.cb
@@ -51,7 +51,6 @@
    register "Cio2Enable" = "0"
    register "SaImguEnable" = "0"
    register "ScsEmmcHs400Enabled" = "1"
-	register "ScsSdCardEnabled" = "2"
    register "PttSwitch" = "0"
    register "SkipExtGfxScan" = "1"
    register "HeciEnabled" = "0"
diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb
index e5307c2..af50156 100644
--- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb
@@ -41,7 +41,6 @@
    register "Cio2Enable" = "1"
    register "SaImguEnable" = "1"
    register "ScsEmmcHs400Enabled" = "1"
-	register "ScsSdCardEnabled" = "2"
    register "PttSwitch" = "0"
    register "SkipExtGfxScan" = "1"
    register "HeciEnabled" = "0"
diff --git a/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb b/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb
index 318986e..8de089d 100644
--- a/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb
+++ b/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb
@@ -26,7 +26,6 @@
    register "HeciEnabled" = "0"
    register "IoBufferOwnership" = "0"
    register "ScsEmmcHs400Enabled" = "1"
-	register "ScsSdCardEnabled" = "2"
    register "SkipExtGfxScan" = "1"
    register "SaGv" = "SaGv_Enabled"
    register "PchHdaVcType" = "Vc1"
diff --git a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb
index ae372ec..fbf08cd 100644
--- a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb
+++ b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb
@@ -3,7 +3,6 @@
    # FSP Configuration
    register "DspEnable" = "0"
    register "ScsEmmcHs400Enabled" = "0"
-	register "ScsSdCardEnabled" = "0"
    register "PmTimerDisabled" = "0"

register "serirq_mode" = "SERIRQ_CONTINUOUS"
diff --git a/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb
index 25dc49e..78552fc 100644
--- a/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb
+++ b/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb
@@ -6,7 +6,6 @@

# FSP Configuration
    register "ScsEmmcHs400Enabled" = "0"
-	register "ScsSdCardEnabled" = "0"
    register "PmTimerDisabled" = "0"

register "serirq_mode" = "SERIRQ_CONTINUOUS"
@@ -171,6 +170,7 @@
    	device pci 1e.2 on  end # GSPI #0
    	device pci 1e.3 on  end # GSPI #1
    	device pci 1e.4 off end # eMMC
+		device pci 1e.6 off end # SDXC
    	device pci 1f.0 on
    		#chip drivers/pc80/tpm
    		#	device pnp 0c31.0 on end
diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb
index ae637ca..2b7a0e3 100644
--- a/src/mainboard/intel/kunimitsu/devicetree.cb
+++ b/src/mainboard/intel/kunimitsu/devicetree.cb
@@ -27,7 +27,6 @@
    register "DspEnable" = "1"
    register "IoBufferOwnership" = "3"
    register "ScsEmmcHs400Enabled" = "1"
-	register "ScsSdCardEnabled" = "2"
    register "SkipExtGfxScan" = "1"
    register "HeciEnabled" = "0"
    register "SaGv" = "SaGv_Enabled"
diff --git a/src/mainboard/intel/saddlebrook/devicetree.cb b/src/mainboard/intel/saddlebrook/devicetree.cb
index 87d3fc0..a25cb8c 100644
--- a/src/mainboard/intel/saddlebrook/devicetree.cb
+++ b/src/mainboard/intel/saddlebrook/devicetree.cb
@@ -21,7 +21,6 @@
    register "DspEnable" = "1"
    register "IoBufferOwnership" = "3"
    register "ScsEmmcHs400Enabled" = "0"
-	register "ScsSdCardEnabled" = "0"
    register "SkipExtGfxScan" = "1"

register "SaGv" = "SaGv_Enabled"
diff --git a/src/mainboard/libretrend/lt1000/devicetree.cb b/src/mainboard/libretrend/lt1000/devicetree.cb
index a355ee4..91552a2 100644
--- a/src/mainboard/libretrend/lt1000/devicetree.cb
+++ b/src/mainboard/libretrend/lt1000/devicetree.cb
@@ -52,7 +52,6 @@
    register "SsicPortEnable" = "0"
    register "Cio2Enable" = "0"
    register "ScsEmmcHs400Enabled" = "0"
-	register "ScsSdCardEnabled" = "0"
    register "SkipExtGfxScan" = "1"
    register "HeciEnabled" = "1"
    register "SaGv" = "SaGv_Enabled"
@@ -201,6 +200,7 @@
    	device pci 1d.1 on  end # PCI Express Port 10
    	device pci 1d.2 on  end # PCI Express Port 11
    	device pci 1d.3 on  end # PCI Express Port 12
+		device pci 1e.6 off end # SDXC
    	device pci 1f.0 on
    		chip drivers/pc80/tpm
    			device pnp 0c31.0 on end
diff --git a/src/mainboard/protectli/vault_kbl/devicetree.cb b/src/mainboard/protectli/vault_kbl/devicetree.cb
index 1640011..63861c6 100644
--- a/src/mainboard/protectli/vault_kbl/devicetree.cb
+++ b/src/mainboard/protectli/vault_kbl/devicetree.cb
@@ -41,7 +41,6 @@
    register "SsicPortEnable" = "0"
    register "Cio2Enable" = "0"
    register "ScsEmmcHs400Enabled" = "0"
-	register "ScsSdCardEnabled" = "0"
    register "SkipExtGfxScan" = "1"
    register "HeciEnabled" = "1"
    register "PmTimerDisabled" = "1"
diff --git a/src/mainboard/purism/librem_skl/devicetree.cb b/src/mainboard/purism/librem_skl/devicetree.cb
index 18e02e7..60f69c8 100644
--- a/src/mainboard/purism/librem_skl/devicetree.cb
+++ b/src/mainboard/purism/librem_skl/devicetree.cb
@@ -57,7 +57,6 @@
    register "SsicPortEnable" = "0"
    register "Cio2Enable" = "0"
    register "ScsEmmcHs400Enabled" = "0"
-	register "ScsSdCardEnabled" = "0"
    register "PttSwitch" = "0"
    register "SkipExtGfxScan" = "1"
    register "HeciEnabled" = "0"
@@ -192,6 +191,7 @@
    	device pci 1d.1 off end # PCI Express Port 10
    	device pci 1d.2 off end # PCI Express Port 11
    	device pci 1d.3 off end # PCI Express Port 12
+		device pci 1e.6 off end # SDXC
    	device pci 1f.0 on
    		chip drivers/pc80/tpm
    			device pnp 0c31.0 on end
diff --git a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb
index 4306da6..6217de5 100644
--- a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb
+++ b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb
@@ -37,7 +37,6 @@
    register "SsicPortEnable" = "0"
    register "Cio2Enable" = "0"
    register "ScsEmmcHs400Enabled" = "0"
-	register "ScsSdCardEnabled" = "0"
    register "PttSwitch" = "0"
    register "SkipExtGfxScan" = "1"
    register "HeciEnabled" = "1"
@@ -228,6 +227,7 @@
    	device pci 1d.2 off end # PCI Express Port 11
    	device pci 1d.3 off end # PCI Express Port 12
    	device pci 1e.0 on  end # Serial IO UART0
+		device pci 1e.6 off end # SDXC
    	device pci 1f.0 on # LPC
    		chip drivers/pc80/tpm
    			device pnp 0c31.0 on end
diff --git a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb
index 435015b..bbc52db 100644
--- a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb
+++ b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb
@@ -8,7 +8,6 @@

# FSP Configuration
    register "ScsEmmcHs400Enabled" = "0"
-	register "ScsSdCardEnabled" = "0"
    register "SkipExtGfxScan" = "1"
    register "SaGv" = "SaGv_Disabled"

@@ -140,6 +139,7 @@
    	device pci 1e.0 off end	# UART #0
    	device pci 1e.1 off end	# UART #1
    	device pci 1e.2 off end	# SPI #0
+		device pci 1e.6 off end # SDXC
    	device pci 1f.0 on	# LPC Interface
    		chip superio/common
    			device pnp 2e.0 on  end
diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c
index 6423cf4..cb0d2fc 100644
--- a/src/soc/intel/skylake/chip.c
+++ b/src/soc/intel/skylake/chip.c
@@ -257,7 +257,9 @@
    dev = pcidev_path_on_root(PCH_DEVFN_EMMC);
    params->ScsEmmcEnabled = dev ? dev->enabled : 0;
    params->ScsEmmcHs400Enabled = config->ScsEmmcHs400Enabled;
-	params->ScsSdCardEnabled = config->ScsSdCardEnabled;
+
+	dev = pcidev_path_on_root(PCH_DEVFN_SDCARD);
+	params->ScsSdCardEnabled = dev && dev->enabled;

if (!!params->ScsEmmcHs400Enabled && !!config->EmmcHs400DllNeed) {
    	params->PchScsEmmcHs400DllDataValid =
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h
index e332a6b..404a9f4 100644
--- a/src/soc/intel/skylake/chip.h
+++ b/src/soc/intel/skylake/chip.h
@@ -306,7 +306,6 @@

/* eMMC and SD */
    u8 ScsEmmcHs400Enabled;
-	u8 ScsSdCardEnabled;
    u8 EmmcHs400DllNeed;
    u8 ScsEmmcHs400RxStrobeDll1;
    u8 ScsEmmcHs400TxDataDll;