New patch to review for coreboot: 5c95341 vendorcode/amd/agesa: Do not hardcode ROM base address
Alexandru Gagniuc (mr.nuke.me@gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5467
-gerrit
commit 5c95341b3d6bf206302adf3234d9694610904ff3 Author: Alexandru Gagniuc mr.nuke.me@gmail.com Date: Sun Apr 6 15:19:56 2014 -0500
vendorcode/amd/agesa: Do not hardcode ROM base address
The ROM address range is set up in the LPC PCI device, register 0x6c. Coreboot already sets that up correctly in the bootblock, however AGESA overrides that to 0xffffff00, which will always map the ROM from 0xff000000. This may conflict with other devices which are assigned address space in that range.
If a device is assigned a range between 0xff000000 and the real ROM base, accesses to that device will be diverted to the system ROM, regardless of how other BARs are set up. Since we already need to set up the ROM address range in the bootblock, before calling AGESA, just remove the override from AGESA.
Note that not all AGESA versions override this mapping.
Change-Id: I592e5d087ed830c9604a04a356912c7654ce56d2 Signed-off-by: Alexandru Gagniuc mr.nuke.me@gmail.com --- src/vendorcode/amd/agesa/f12/Proc/Fch/Spi/LpcReset.c | 2 -- .../agesa/f15tn/Proc/Fch/Spi/Family/Hudson2/Hudson2LpcResetService.c | 2 -- .../agesa/f16kb/Proc/Fch/Spi/Family/Yangtze/YangtzeLpcResetService.c | 2 -- 3 files changed, 6 deletions(-)
diff --git a/src/vendorcode/amd/agesa/f12/Proc/Fch/Spi/LpcReset.c b/src/vendorcode/amd/agesa/f12/Proc/Fch/Spi/LpcReset.c index 8e9bee7..e4aca36 100644 --- a/src/vendorcode/amd/agesa/f12/Proc/Fch/Spi/LpcReset.c +++ b/src/vendorcode/amd/agesa/f12/Proc/Fch/Spi/LpcReset.c @@ -98,8 +98,6 @@ FchInitResetLpc ( // RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REGBA, AccessWidth16, 0xFFFF, BIT8, StdHeader);
- RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REG6C, AccessWidth32, 0xFFFFFF00, 0, StdHeader); - ProgramPciByteTable ( (REG8_MASK*) (&FchInitResetLpcPciTable[0]), sizeof (FchInitResetLpcPciTable) / sizeof (REG8_MASK), StdHeader);
if ( LocalCfgPtr->LegacyFree ) { diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Spi/Family/Hudson2/Hudson2LpcResetService.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Spi/Family/Hudson2/Hudson2LpcResetService.c index adbfab3..36259d3 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Spi/Family/Hudson2/Hudson2LpcResetService.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Spi/Family/Hudson2/Hudson2LpcResetService.c @@ -99,8 +99,6 @@ FchInitResetLpcProgram ( // RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REGBA, AccessWidth16, 0xFFFF, BIT8, StdHeader);
- RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REG6C, AccessWidth32, 0xFFFFFF00, 0, StdHeader); - ProgramPciByteTable ( (REG8_MASK*) (&FchInitHudson2ResetLpcPciTable[0]), sizeof (FchInitHudson2ResetLpcPciTable) / sizeof (REG8_MASK), StdHeader);
// diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Spi/Family/Yangtze/YangtzeLpcResetService.c b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Spi/Family/Yangtze/YangtzeLpcResetService.c index 1a02218..ab71bb9 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Spi/Family/Yangtze/YangtzeLpcResetService.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/Fch/Spi/Family/Yangtze/YangtzeLpcResetService.c @@ -125,8 +125,6 @@ FchInitResetLpcProgram ( // RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REGBA, AccessWidth16, 0xFFFF, BIT8, StdHeader);
- RwPci ((LPC_BUS_DEV_FUN << 16) + FCH_LPC_REG6C, AccessWidth32, 0xFFFFFF00, 0, StdHeader); - ProgramPciByteTable ( (REG8_MASK*) (&FchInitYangtzeResetLpcPciTable[0]), sizeof (FchInitYangtzeResetLpcPciTable) / sizeof (REG8_MASK), StdHeader);
if ( LocalCfgPtr->Spi.LpcClk0 ) {
-
Alexandru Gagniuc