Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34336 )
Change subject: sb/intel/bd82x6x: Add support to disable xHCI ......................................................................
sb/intel/bd82x6x: Add support to disable xHCI
Set FD bit if xHCI is disabled in devicetree.
Change-Id: I3d08ded10daea6d86857ebbbf3f8dcc85ebe9df4 Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com --- M src/southbridge/intel/bd82x6x/pch.c 1 file changed, 4 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/34336/1
diff --git a/src/southbridge/intel/bd82x6x/pch.c b/src/southbridge/intel/bd82x6x/pch.c index f8540af..3f7c75e 100644 --- a/src/southbridge/intel/bd82x6x/pch.c +++ b/src/southbridge/intel/bd82x6x/pch.c @@ -148,6 +148,10 @@ static void pch_hide_devfn(unsigned devfn) { switch (devfn) { + case PCI_DEVFN(20, 0): /* xHCI */ + if (pch_silicon_type() == PCH_TYPE_PPT) + RCBA32_OR(FD, PCH_DISABLE_XHCI); + break; case PCI_DEVFN(22, 0): /* MEI #1 */ RCBA32_OR(FD2, PCH_DISABLE_MEI1); break;
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34336 )
Change subject: sb/intel/bd82x6x: Add support to disable xHCI ......................................................................
Patch Set 3: Code-Review+1
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34336 )
Change subject: sb/intel/bd82x6x: Add support to disable xHCI ......................................................................
Patch Set 4: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/34336/4/src/southbridge/intel/bd82x... File src/southbridge/intel/bd82x6x/pch.c:
https://review.coreboot.org/c/coreboot/+/34336/4/src/southbridge/intel/bd82x... PS4, Line 152: if (pch_silicon_type() == PCH_TYPE_PPT) I'd prefer to have brackets around the next line
Hello Alexander Couzens, Evgeny Zinoviev, Patrick Rudolph, Alexey Derlaft, Felix Held, Paul Menzel, Philipp Deppenwiese, build bot (Jenkins), Bill XIE, Marcello Sylvester Bauer,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34336
to look at the new patch set (#5).
Change subject: sb/intel/bd82x6x: Add support to disable xHCI ......................................................................
sb/intel/bd82x6x: Add support to disable xHCI
Set FD bit if xHCI is disabled in devicetree.
Change-Id: I3d08ded10daea6d86857ebbbf3f8dcc85ebe9df4 Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com --- M src/southbridge/intel/bd82x6x/pch.c 1 file changed, 6 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/34336/5
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34336 )
Change subject: sb/intel/bd82x6x: Add support to disable xHCI ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34336/4/src/southbridge/intel/bd82x... File src/southbridge/intel/bd82x6x/pch.c:
https://review.coreboot.org/c/coreboot/+/34336/4/src/southbridge/intel/bd82x... PS4, Line 152: if (pch_silicon_type() == PCH_TYPE_PPT)
I'd prefer to have brackets around the next line
Done
Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34336 )
Change subject: sb/intel/bd82x6x: Add support to disable xHCI ......................................................................
Patch Set 5: Code-Review+2
Felix Held has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/34336 )
Change subject: sb/intel/bd82x6x: Add support to disable xHCI ......................................................................
sb/intel/bd82x6x: Add support to disable xHCI
Set FD bit if xHCI is disabled in devicetree.
Change-Id: I3d08ded10daea6d86857ebbbf3f8dcc85ebe9df4 Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/34336 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Felix Held felix-coreboot@felixheld.de --- M src/southbridge/intel/bd82x6x/pch.c 1 file changed, 6 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved
diff --git a/src/southbridge/intel/bd82x6x/pch.c b/src/southbridge/intel/bd82x6x/pch.c index f8540af..e4eccd7 100644 --- a/src/southbridge/intel/bd82x6x/pch.c +++ b/src/southbridge/intel/bd82x6x/pch.c @@ -148,6 +148,12 @@ static void pch_hide_devfn(unsigned devfn) { switch (devfn) { + case PCI_DEVFN(20, 0): /* xHCI */ + if (pch_silicon_type() == PCH_TYPE_PPT) { + /* on CPT this bit is reserved */ + RCBA32_OR(FD, PCH_DISABLE_XHCI); + } + break; case PCI_DEVFN(22, 0): /* MEI #1 */ RCBA32_OR(FD2, PCH_DISABLE_MEI1); break;