Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30973
Change subject: src/mainboard/sony: Add Sony VPCEH2K1E ......................................................................
src/mainboard/sony: Add Sony VPCEH2K1E
Run autoport. It has a Nvidia graphics card and a Nuvoton NPCE795 EC.
Change-Id: Ibf324f1276611ab06d5906cab87ad538bfad7218 Signed-off-by: Angel Pons th3fanbus@gmail.com --- A src/mainboard/sony/vpceh2k1e/Kconfig A src/mainboard/sony/vpceh2k1e/Kconfig.name A src/mainboard/sony/vpceh2k1e/Makefile.inc A src/mainboard/sony/vpceh2k1e/acpi/ec.asl A src/mainboard/sony/vpceh2k1e/acpi/platform.asl A src/mainboard/sony/vpceh2k1e/acpi/superio.asl A src/mainboard/sony/vpceh2k1e/acpi_tables.c A src/mainboard/sony/vpceh2k1e/board_info.txt A src/mainboard/sony/vpceh2k1e/devicetree.cb A src/mainboard/sony/vpceh2k1e/dsdt.asl A src/mainboard/sony/vpceh2k1e/gpio.c A src/mainboard/sony/vpceh2k1e/hda_verb.c A src/mainboard/sony/vpceh2k1e/mainboard.c A src/mainboard/sony/vpceh2k1e/romstage.c 14 files changed, 700 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/30973/1
diff --git a/src/mainboard/sony/vpceh2k1e/Kconfig b/src/mainboard/sony/vpceh2k1e/Kconfig new file mode 100644 index 0000000..7d1f6ca --- /dev/null +++ b/src/mainboard/sony/vpceh2k1e/Kconfig @@ -0,0 +1,44 @@ +if BOARD_SONY_VPCEH2K1E + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_4096 + select CPU_INTEL_SOCKET_RPGA989 + select EC_ACPI + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_INT15 + select NORTHBRIDGE_INTEL_SANDYBRIDGE + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_BD82X6X + select SYSTEM_TYPE_LAPTOP + select USE_NATIVE_RAMINIT + +config MAINBOARD_DIR + string + default sony_corporation/vpceh2k1e + +config MAINBOARD_PART_NUMBER + string + default "VPCEH2K1E" + +config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID + hex + default 0x908b + +config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID + hex + default 0x104d + +config DRAM_RESET_GATE_GPIO # FIXME: check this + int + default 60 + +config MAX_CPUS + int + default 8 + +config USBDEBUG_HCD_INDEX # FIXME: check this + int + default 2 +endif diff --git a/src/mainboard/sony/vpceh2k1e/Kconfig.name b/src/mainboard/sony/vpceh2k1e/Kconfig.name new file mode 100644 index 0000000..3de2fcc --- /dev/null +++ b/src/mainboard/sony/vpceh2k1e/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_SONY_VPCEH2K1E + bool "VPCEH2K1E" diff --git a/src/mainboard/sony/vpceh2k1e/Makefile.inc b/src/mainboard/sony/vpceh2k1e/Makefile.inc new file mode 100644 index 0000000..3dae61e --- /dev/null +++ b/src/mainboard/sony/vpceh2k1e/Makefile.inc @@ -0,0 +1 @@ +romstage-y += gpio.c diff --git a/src/mainboard/sony/vpceh2k1e/acpi/ec.asl b/src/mainboard/sony/vpceh2k1e/acpi/ec.asl new file mode 100644 index 0000000..9988369 --- /dev/null +++ b/src/mainboard/sony/vpceh2k1e/acpi/ec.asl @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Angel Pons th3fanbus@gmail.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Device(EC) +{ + Name (_HID, EISAID("PNP0C09")) + Name (_UID, 0) + Name (_GPE, 23) +/* FIXME: EC support */ +} diff --git a/src/mainboard/sony/vpceh2k1e/acpi/platform.asl b/src/mainboard/sony/vpceh2k1e/acpi/platform.asl new file mode 100644 index 0000000..15d53d9 --- /dev/null +++ b/src/mainboard/sony/vpceh2k1e/acpi/platform.asl @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Angel Pons th3fanbus@gmail.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Method(_WAK,1) +{ + /* FIXME: EC support */ + Return(Package(){0,0}) +} + +Method(_PTS,1) +{ + /* FIXME: EC support */ +} diff --git a/src/mainboard/sony/vpceh2k1e/acpi/superio.asl b/src/mainboard/sony/vpceh2k1e/acpi/superio.asl new file mode 100644 index 0000000..8bfc1a0 --- /dev/null +++ b/src/mainboard/sony/vpceh2k1e/acpi/superio.asl @@ -0,0 +1,17 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Angel Pons th3fanbus@gmail.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <drivers/pc80/pc/ps2_controller.asl> diff --git a/src/mainboard/sony/vpceh2k1e/acpi_tables.c b/src/mainboard/sony/vpceh2k1e/acpi_tables.c new file mode 100644 index 0000000..7d634a0 --- /dev/null +++ b/src/mainboard/sony/vpceh2k1e/acpi_tables.c @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/bd82x6x/nvs.h> + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + /* Disable USB ports in S3 by default */ + gnvs->s3u0 = 0; + gnvs->s3u1 = 0; + + /* Disable USB ports in S5 by default */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; + + // the lid is open by default. + gnvs->lids = 1; + + gnvs->tcrt = 100; + gnvs->tpsv = 90; +} diff --git a/src/mainboard/sony/vpceh2k1e/board_info.txt b/src/mainboard/sony/vpceh2k1e/board_info.txt new file mode 100644 index 0000000..689ca8f --- /dev/null +++ b/src/mainboard/sony/vpceh2k1e/board_info.txt @@ -0,0 +1,5 @@ +Category: laptop +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: n diff --git a/src/mainboard/sony/vpceh2k1e/devicetree.cb b/src/mainboard/sony/vpceh2k1e/devicetree.cb new file mode 100644 index 0000000..d96ae12 --- /dev/null +++ b/src/mainboard/sony/vpceh2k1e/devicetree.cb @@ -0,0 +1,63 @@ +chip northbridge/intel/sandybridge # FIXME: check gfx.ndid and gfx.did + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }" + register "gfx.ndid" = "3" + device cpu_cluster 0x0 on + chip cpu/intel/socket_rPGA989 + device lapic 0x0 on + end + end + chip cpu/intel/model_206ax + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + device lapic 0xacac off + end + end + end + device domain 0x0 on + subsystemid 0x104d 0x908b inherit + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "c2_latency" = "0x0065" + register "docking_supported" = "1" + register "gen1_dec" = "0x000c0601" + register "gen2_dec" = "0x000c1641" + register "gen3_dec" = "0x00040069" + register "gpi7_routing" = "2" + register "p_cnt_throttling_supported" = "1" + register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }" + register "pcie_port_coalesce" = "1" + register "sata_interface_speed_support" = "0x3" + register "sata_port_map" = "0x9" + register "spi_lvscc" = "0x2005" + register "spi_uvscc" = "0x2005" + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 19.0 off end # Intel Gigabit Ethernet + device pci 1a.0 on end # USB2 EHCI #2 + device pci 1b.0 on end # High Definition Audio Audio controller + device pci 1c.0 on end # PCIe Port #1 + device pci 1c.1 off end # PCIe Port #2 + device pci 1c.2 off end # PCIe Port #3 + device pci 1c.3 on end # PCIe Port #4 + device pci 1c.4 off end # PCIe Port #5 + device pci 1c.5 on end # PCIe Port #6 + device pci 1c.6 off end # PCIe Port #7 + device pci 1c.7 off end # PCIe Port #8 + device pci 1d.0 on end # USB2 EHCI #1 + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on end # LPC bridge PCI-LPC bridge + device pci 1f.2 on end # SATA Controller 1 + device pci 1f.3 on end # SMBus + device pci 1f.5 off end # SATA Controller 2 + device pci 1f.6 off end # Thermal + end + device pci 00.0 on end # Host bridge + device pci 01.0 on end # PCIe Bridge for discrete graphics + device pci 02.0 off end # Internal graphics + end +end diff --git a/src/mainboard/sony/vpceh2k1e/dsdt.asl b/src/mainboard/sony/vpceh2k1e/dsdt.asl new file mode 100644 index 0000000..675703b --- /dev/null +++ b/src/mainboard/sony/vpceh2k1e/dsdt.asl @@ -0,0 +1,46 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Angel Pons th3fanbus@gmail.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define BRIGHTNESS_UP _SB.PCI0.GFX0.INCB +#define BRIGHTNESS_DOWN _SB.PCI0.GFX0.DECB +#define ACPI_VIDEO_DEVICE _SB.PCI0.GFX0 + +#include <arch/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI 2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 // OEM revision +) +{ + /* Some generic macros */ + #include "acpi/platform.asl" + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/bd82x6x/acpi/platform.asl> + + /* global NVS and variables. */ + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> + + Device (_SB.PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + } +} diff --git a/src/mainboard/sony/vpceh2k1e/gpio.c b/src/mainboard/sony/vpceh2k1e/gpio.c new file mode 100644 index 0000000..5a16e8e --- /dev/null +++ b/src/mainboard/sony/vpceh2k1e/gpio.c @@ -0,0 +1,235 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_GPIO, + .gpio10 = GPIO_MODE_GPIO, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_GPIO, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_GPIO, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_GPIO, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio9 = GPIO_DIR_INPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio18 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio20 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio23 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_INPUT, + .gpio26 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_INPUT, + .gpio29 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio24 = GPIO_RESET_RSMRST, + .gpio30 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio1 = GPIO_INVERT, + .gpio2 = GPIO_INVERT, + .gpio3 = GPIO_INVERT, + .gpio4 = GPIO_INVERT, + .gpio5 = GPIO_INVERT, + .gpio7 = GPIO_INVERT, + .gpio9 = GPIO_INVERT, + .gpio10 = GPIO_INVERT, + .gpio11 = GPIO_INVERT, + .gpio12 = GPIO_INVERT, + .gpio14 = GPIO_INVERT, + .gpio15 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_NATIVE, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_GPIO, + .gpio42 = GPIO_MODE_GPIO, + .gpio43 = GPIO_MODE_GPIO, + .gpio44 = GPIO_MODE_GPIO, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_GPIO, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_GPIO, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_GPIO, + .gpio61 = GPIO_MODE_GPIO, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio33 = GPIO_DIR_INPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_INPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio41 = GPIO_DIR_INPUT, + .gpio42 = GPIO_DIR_INPUT, + .gpio43 = GPIO_DIR_INPUT, + .gpio44 = GPIO_DIR_INPUT, + .gpio46 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_OUTPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_INPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_INPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_INPUT, + .gpio56 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, + .gpio60 = GPIO_DIR_OUTPUT, + .gpio61 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio49 = GPIO_LEVEL_HIGH, + .gpio60 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_GPIO, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_GPIO, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio64 = GPIO_DIR_INPUT, + .gpio66 = GPIO_DIR_INPUT, + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_INPUT, + .gpio71 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/sony/vpceh2k1e/hda_verb.c b/src/mainboard/sony/vpceh2k1e/hda_verb.c new file mode 100644 index 0000000..d2c4fa3 --- /dev/null +++ b/src/mainboard/sony/vpceh2k1e/hda_verb.c @@ -0,0 +1,61 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x14f1506e, /* Codec Vendor / Device ID: Conexant */ + 0x104d5a00, /* Subsystem ID */ + + 0x0000000b, /* Number of 4 dword sets */ + /* NID 0x01: Subsystem ID. */ + AZALIA_SUBVENDOR(0x0, 0x104d5a00), + + /* NID 0x19. */ + AZALIA_PIN_CFG(0x0, 0x19, 0x03211040), + + /* NID 0x1a. */ + AZALIA_PIN_CFG(0x0, 0x1a, 0x400001f0), + + /* NID 0x1b. */ + AZALIA_PIN_CFG(0x0, 0x1b, 0x03a15030), + + /* NID 0x1c. */ + AZALIA_PIN_CFG(0x0, 0x1c, 0x400001f0), + + /* NID 0x1d. */ + AZALIA_PIN_CFG(0x0, 0x1d, 0x400001f0), + + /* NID 0x1e. */ + AZALIA_PIN_CFG(0x0, 0x1e, 0x400001f0), + + /* NID 0x1f. */ + AZALIA_PIN_CFG(0x0, 0x1f, 0x90170110), + + /* NID 0x20. */ + AZALIA_PIN_CFG(0x0, 0x20, 0x400001f0), + + /* NID 0x22. */ + AZALIA_PIN_CFG(0x0, 0x22, 0x400001f0), + + /* NID 0x23. */ + AZALIA_PIN_CFG(0x0, 0x23, 0x90a70150), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/sony/vpceh2k1e/mainboard.c b/src/mainboard/sony/vpceh2k1e/mainboard.c new file mode 100644 index 0000000..08cb738 --- /dev/null +++ b/src/mainboard/sony/vpceh2k1e/mainboard.c @@ -0,0 +1,63 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Angel Pons th3fanbus@gmail.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <drivers/intel/gma/int15.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <ec/acpi/ec.h> +#include <console/console.h> +#include <pc80/keyboard.h> + +static void mainboard_init(struct device *dev) +{ + /* FIXME: trim this down or remove if necessary */ + if (0) { + int i; + const u8 dmp[256] = { + /* 00 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x94, 0x94, 0x94, 0x94, 0x94, 0x94, + /* 10 */ 0x94, 0x94, 0x05, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 20 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 30 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x14, 0xc0, 0x00, + /* 40 */ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 50 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x00, 0x2d, 0x29, 0x00, 0x31, 0x00, 0x00, 0x00, 0x00, + /* 60 */ 0x41, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x6e, 0x0a, 0x28, 0x0a, 0x01, 0x01, 0x26, 0x00, 0x00, 0x00, + /* 70 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 80 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 90 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* a0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* b0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* c0 */ 0x10, 0x02, 0x00, 0x00, 0x09, 0x4a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x44, + /* d0 */ 0x00, 0xff, 0x00, 0x00, 0x01, 0x00, 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x0b, 0x1a, + /* e0 */ 0x28, 0x28, 0x28, 0x00, 0x00, 0x00, 0x58, 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* f0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, + }; + + printk(BIOS_DEBUG, "Replaying EC dump ..."); + for (i = 0; i < 256; i++) + ec_write (i, dmp[i]); + printk(BIOS_DEBUG, "done\n"); + } + pc_keyboard_init(NO_AUX_DEVICE); +} + +static void mainboard_enable(struct device *dev) +{ + dev->ops->init = mainboard_init; +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/sony/vpceh2k1e/romstage.c b/src/mainboard/sony/vpceh2k1e/romstage.c new file mode 100644 index 0000000..0e1c365 --- /dev/null +++ b/src/mainboard/sony/vpceh2k1e/romstage.c @@ -0,0 +1,79 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <string.h> +#include <lib.h> +#include <timestamp.h> +#include <arch/byteorder.h> +#include <arch/io.h> +#include <device/pci_def.h> +#include <device/pnp_def.h> +#include <cpu/x86/lapic.h> +#include <arch/acpi.h> +#include <console/console.h> +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/common/gpio.h> +#include <arch/cpu.h> +#include <cpu/x86/msr.h> + +void pch_enable_lpc(void) +{ + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x1c01); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x000c0601); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x000c1641); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x00040069); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00000000); + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010); +} + +void mainboard_rcba_config(void) +{ +} + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 1, 0 }, + { 1, 1, 1 }, + { 1, 1, 2 }, + { 0, 1, -1 }, + { 1, 1, 3 }, + { 0, 0, -1 }, + { 0, 0, -1 }, + { 0, 0, -1 }, + { 0, 1, -1 }, + { 1, 0, -1 }, + { 0, 0, -1 }, + { 0, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, +}; + +void mainboard_early_init(int s3resume) +{ +} + +void mainboard_config_superio(void) +{ +} + +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[2], 0x52, id_only); +}
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30973 )
Change subject: src/mainboard/sony: Add Sony VPCEH2K1E ......................................................................
Patch Set 1:
(17 comments)
https://review.coreboot.org/#/c/30973/1/src/mainboard/sony/vpceh2k1e/mainboa... File src/mainboard/sony/vpceh2k1e/mainboard.c:
https://review.coreboot.org/#/c/30973/1/src/mainboard/sony/vpceh2k1e/mainboa... PS1, Line 30: /* 00 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x94, 0x94, 0x94, 0x94, 0x94, 0x94, line over 80 characters
https://review.coreboot.org/#/c/30973/1/src/mainboard/sony/vpceh2k1e/mainboa... PS1, Line 31: /* 10 */ 0x94, 0x94, 0x05, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, line over 80 characters
https://review.coreboot.org/#/c/30973/1/src/mainboard/sony/vpceh2k1e/mainboa... PS1, Line 32: /* 20 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, line over 80 characters
https://review.coreboot.org/#/c/30973/1/src/mainboard/sony/vpceh2k1e/mainboa... PS1, Line 33: /* 30 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x14, 0xc0, 0x00, line over 80 characters
https://review.coreboot.org/#/c/30973/1/src/mainboard/sony/vpceh2k1e/mainboa... PS1, Line 34: /* 40 */ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, line over 80 characters
https://review.coreboot.org/#/c/30973/1/src/mainboard/sony/vpceh2k1e/mainboa... PS1, Line 35: /* 50 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x00, 0x2d, 0x29, 0x00, 0x31, 0x00, 0x00, 0x00, 0x00, line over 80 characters
https://review.coreboot.org/#/c/30973/1/src/mainboard/sony/vpceh2k1e/mainboa... PS1, Line 36: /* 60 */ 0x41, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x6e, 0x0a, 0x28, 0x0a, 0x01, 0x01, 0x26, 0x00, 0x00, 0x00, line over 80 characters
https://review.coreboot.org/#/c/30973/1/src/mainboard/sony/vpceh2k1e/mainboa... PS1, Line 37: /* 70 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, line over 80 characters
https://review.coreboot.org/#/c/30973/1/src/mainboard/sony/vpceh2k1e/mainboa... PS1, Line 38: /* 80 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, line over 80 characters
https://review.coreboot.org/#/c/30973/1/src/mainboard/sony/vpceh2k1e/mainboa... PS1, Line 39: /* 90 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, line over 80 characters
https://review.coreboot.org/#/c/30973/1/src/mainboard/sony/vpceh2k1e/mainboa... PS1, Line 40: /* a0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, line over 80 characters
https://review.coreboot.org/#/c/30973/1/src/mainboard/sony/vpceh2k1e/mainboa... PS1, Line 41: /* b0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, line over 80 characters
https://review.coreboot.org/#/c/30973/1/src/mainboard/sony/vpceh2k1e/mainboa... PS1, Line 42: /* c0 */ 0x10, 0x02, 0x00, 0x00, 0x09, 0x4a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x44, line over 80 characters
https://review.coreboot.org/#/c/30973/1/src/mainboard/sony/vpceh2k1e/mainboa... PS1, Line 43: /* d0 */ 0x00, 0xff, 0x00, 0x00, 0x01, 0x00, 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x0b, 0x1a, line over 80 characters
https://review.coreboot.org/#/c/30973/1/src/mainboard/sony/vpceh2k1e/mainboa... PS1, Line 44: /* e0 */ 0x28, 0x28, 0x28, 0x00, 0x00, 0x00, 0x58, 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, line over 80 characters
https://review.coreboot.org/#/c/30973/1/src/mainboard/sony/vpceh2k1e/mainboa... PS1, Line 45: /* f0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, line over 80 characters
https://review.coreboot.org/#/c/30973/1/src/mainboard/sony/vpceh2k1e/mainboa... PS1, Line 50: ec_write (i, dmp[i]); space prohibited between function name and open parenthesis '('
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30973 )
Change subject: [WIP] src/mainboard/sony: Add Sony VPCEH2K1E ......................................................................
Patch Set 3:
This port is mostly functional, with suspend/resume, keyboard and touchpad working. It is missing any battery support, however (I don't have one to test it with, anyway)
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30973 )
Change subject: [WIP] src/mainboard/sony: Add Sony VPCEH2K1E ......................................................................
Patch Set 3:
(5 comments)
Notes to self:
https://review.coreboot.org/#/c/30973/3/src/mainboard/sony/vpceh2k1e/Kconfig File src/mainboard/sony/vpceh2k1e/Kconfig:
https://review.coreboot.org/#/c/30973/3/src/mainboard/sony/vpceh2k1e/Kconfig... PS3, Line 33: Specify Nvidia GPU's PCI ID here for the VBIOS
https://review.coreboot.org/#/c/30973/3/src/mainboard/sony/vpceh2k1e/devicet... File src/mainboard/sony/vpceh2k1e/devicetree.cb:
https://review.coreboot.org/#/c/30973/3/src/mainboard/sony/vpceh2k1e/devicet... PS3, Line 5: chip cpu/intel/socket_rPGA989 : device lapic 0x0 on : end : end Recent patch changes this
https://review.coreboot.org/#/c/30973/3/src/mainboard/sony/vpceh2k1e/dsdt.as... File src/mainboard/sony/vpceh2k1e/dsdt.asl:
https://review.coreboot.org/#/c/30973/3/src/mainboard/sony/vpceh2k1e/dsdt.as... PS3, Line 21: #include <arch/acpi.h> Space afterwards
https://review.coreboot.org/#/c/30973/3/src/mainboard/sony/vpceh2k1e/dsdt.as... PS3, Line 31: /* Some generic macros */ Banish
https://review.coreboot.org/#/c/30973/3/src/mainboard/sony/vpceh2k1e/mainboa... File src/mainboard/sony/vpceh2k1e/mainboard.c:
https://review.coreboot.org/#/c/30973/3/src/mainboard/sony/vpceh2k1e/mainboa... PS3, Line 26: remove Banish
Hello build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/30973
to look at the new patch set (#4).
Change subject: src/mainboard/sony: Add Sony VPCEH2K1E ......................................................................
src/mainboard/sony: Add Sony VPCEH2K1E
Run autoport. It has a Nvidia graphics card and a Nuvoton NPCE795 EC. It boots fine with the VGA BIOS, EHCI debug is on the front right USB port, HDMI should work, all PCI devices are found. EC firmware is shared with the main flash chip, it is a chunk of 128KiB at the beginning of the BIOS region. The power button works, automatic fan control is working as well. Keyboard works, brightness keys do NOT work though! Touchpad works too.
EC ACPI SUPPORT MISSING!
Everything else is untested!
Change-Id: Ibf324f1276611ab06d5906cab87ad538bfad7218 Signed-off-by: Angel Pons th3fanbus@gmail.com --- A src/mainboard/sony/Kconfig A src/mainboard/sony/Kconfig.name A src/mainboard/sony/vpceh2k1e/Kconfig A src/mainboard/sony/vpceh2k1e/Kconfig.name A src/mainboard/sony/vpceh2k1e/Makefile.inc A src/mainboard/sony/vpceh2k1e/acpi/ec.asl A src/mainboard/sony/vpceh2k1e/acpi/platform.asl A src/mainboard/sony/vpceh2k1e/acpi/superio.asl A src/mainboard/sony/vpceh2k1e/acpi_tables.c A src/mainboard/sony/vpceh2k1e/board_info.txt A src/mainboard/sony/vpceh2k1e/devicetree.cb A src/mainboard/sony/vpceh2k1e/dsdt.asl A src/mainboard/sony/vpceh2k1e/gpio.c A src/mainboard/sony/vpceh2k1e/hda_verb.c A src/mainboard/sony/vpceh2k1e/mainboard.c A src/mainboard/sony/vpceh2k1e/romstage.c 16 files changed, 706 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/30973/4
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30973 )
Change subject: src/mainboard/sony: Add Sony VPCEH2K1E ......................................................................
Patch Set 4:
(6 comments)
https://review.coreboot.org/#/c/30973/4//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/30973/4//COMMIT_MSG@12 PS4, Line 12: EC firmware is shared with the main flash chip, it is a chunk of 128KiB you probably want a custom fmap file to deal with that properly or at least set a cbfssize in Kconfig also mentioning this.
https://review.coreboot.org/#/c/30973/4//COMMIT_MSG@14 PS4, Line 14: brightness keys do NOT : work though! You can get it merged without that, but look for _Qxx methods in the vendor DSDT that implements it.
https://review.coreboot.org/#/c/30973/4/src/mainboard/sony/vpceh2k1e/romstag... File src/mainboard/sony/vpceh2k1e/romstage.c:
https://review.coreboot.org/#/c/30973/4/src/mainboard/sony/vpceh2k1e/romstag... PS4, Line 38: 0x1c01 use macros in sb/intel/bd82x6x/pch.h
https://review.coreboot.org/#/c/30973/4/src/mainboard/sony/vpceh2k1e/romstag... PS4, Line 38: 0x82 LPC_EN
https://review.coreboot.org/#/c/30973/4/src/mainboard/sony/vpceh2k1e/romstag... PS4, Line 40: pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x000c1641); use LPC_GENx_DEC
https://review.coreboot.org/#/c/30973/4/src/mainboard/sony/vpceh2k1e/romstag... PS4, Line 42: 0x80 LPC_IO_DEC
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30973 )
Change subject: src/mainboard/sony: Add Sony VPCEH2K1E ......................................................................
Patch Set 4:
(4 comments)
https://review.coreboot.org/#/c/30973/4//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/30973/4//COMMIT_MSG@12 PS4, Line 12: EC firmware is shared with the main flash chip, it is a chunk of 128KiB
you probably want a custom fmap file to deal with that properly or at least set a cbfssize in Kconfi […]
Alright, I'll need to check how to work with fmaps. Regarding cbfssize, the BIOS region is 2MiB, but these 128 KiB are taken by the EC firmware
https://review.coreboot.org/#/c/30973/4//COMMIT_MSG@14 PS4, Line 14: brightness keys do NOT : work though!
You can get it merged without that, but look for _Qxx methods in the vendor DSDT that implements it.
Right now not even the EC data/cmd ports are visible in /proc/ioports... The backlight itself works btw.
https://review.coreboot.org/#/c/30973/4/src/mainboard/sony/vpceh2k1e/romstag... File src/mainboard/sony/vpceh2k1e/romstage.c:
https://review.coreboot.org/#/c/30973/4/src/mainboard/sony/vpceh2k1e/romstag... PS4, Line 38: 0x82
LPC_EN
Right... Remind myself to fix these in autopork
https://review.coreboot.org/#/c/30973/4/src/mainboard/sony/vpceh2k1e/romstag... PS4, Line 40: pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x000c1641);
use LPC_GENx_DEC
Should LPC_GENx_DEC be set here, in devicetree or both?
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30973 )
Change subject: src/mainboard/sony: Add Sony VPCEH2K1E ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/#/c/30973/4/src/mainboard/sony/vpceh2k1e/romstag... File src/mainboard/sony/vpceh2k1e/romstage.c:
https://review.coreboot.org/#/c/30973/4/src/mainboard/sony/vpceh2k1e/romstag... PS4, Line 40: pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x000c1641);
Should LPC_GENx_DEC be set here, in devicetree or both?
if you don't need to access those IO ranges in the romstage you should remove it here.
Hello build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/30973
to look at the new patch set (#5).
Change subject: src/mainboard/sony: Add Sony VPCEH2K1E ......................................................................
src/mainboard/sony: Add Sony VPCEH2K1E
Run autoport. It has a Nvidia graphics card and a Nuvoton NPCE795 EC. It boots fine with the VGA BIOS, EHCI debug is on the front right USB port, HDMI should work, all PCI devices are found. EC firmware is shared with the main flash chip, it is a chunk of 128KiB at the beginning of the BIOS region. The power button works, automatic fan control is working as well. Keyboard works, brightness keys do NOT work though! Touchpad works too.
EC ACPI SUPPORT STILL WIP!
Everything else is untested!
TODO: Use FMAP to put EC firmware in its place
Change-Id: Ibf324f1276611ab06d5906cab87ad538bfad7218 Signed-off-by: Angel Pons th3fanbus@gmail.com --- A src/mainboard/sony/Kconfig A src/mainboard/sony/Kconfig.name A src/mainboard/sony/vpceh2k1e/Kconfig A src/mainboard/sony/vpceh2k1e/Kconfig.name A src/mainboard/sony/vpceh2k1e/Makefile.inc A src/mainboard/sony/vpceh2k1e/acpi/ec.asl A src/mainboard/sony/vpceh2k1e/acpi/platform.asl A src/mainboard/sony/vpceh2k1e/acpi/superio.asl A src/mainboard/sony/vpceh2k1e/acpi/thermal.asl A src/mainboard/sony/vpceh2k1e/acpi_tables.c A src/mainboard/sony/vpceh2k1e/board_info.txt A src/mainboard/sony/vpceh2k1e/devicetree.cb A src/mainboard/sony/vpceh2k1e/dsdt.asl A src/mainboard/sony/vpceh2k1e/gpio.c A src/mainboard/sony/vpceh2k1e/hda_verb.c A src/mainboard/sony/vpceh2k1e/mainboard.c A src/mainboard/sony/vpceh2k1e/romstage.c 17 files changed, 1,784 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/30973/5
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30973 )
Change subject: src/mainboard/sony: Add Sony VPCEH2K1E ......................................................................
Patch Set 5: Code-Review-1
License headers are wrong
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30973 )
Change subject: src/mainboard/sony: Add Sony VPCEH2K1E ......................................................................
Patch Set 5:
(2 comments)
https://review.coreboot.org/#/c/30973/5//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/30973/5//COMMIT_MSG@21 PS5, Line 21: TODO: Use FMAP to put EC firmware in its place Tested, required.
https://review.coreboot.org/#/c/30973/5/src/mainboard/sony/vpceh2k1e/romstag... File src/mainboard/sony/vpceh2k1e/romstage.c:
https://review.coreboot.org/#/c/30973/5/src/mainboard/sony/vpceh2k1e/romstag... PS5, Line 17: #include <device/pci_ops.h> #include <device/pnp_ops.h>
Hello build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/30973
to look at the new patch set (#6).
Change subject: src/mainboard/sony: Add Sony VPCEH2K1E ......................................................................
src/mainboard/sony: Add Sony VPCEH2K1E
Run autoport. It has a Nvidia graphics card and a Nuvoton NPCE795 EC. It boots fine with the VGA BIOS, EHCI debug is on the front right USB port, HDMI should work, all PCI devices are found. EC firmware is shared with the main flash chip, it is a chunk of 128KiB at the beginning of the BIOS region. The power button works, automatic fan control is working as well. Keyboard works, brightness keys do NOT work though! Touchpad works too.
EC ACPI SUPPORT STILL WIP!
Everything else is untested!
TODO: Use FMAP to put EC firmware in its place
Change-Id: Ibf324f1276611ab06d5906cab87ad538bfad7218 Signed-off-by: Angel Pons th3fanbus@gmail.com --- A src/mainboard/sony/Kconfig A src/mainboard/sony/Kconfig.name A src/mainboard/sony/vpceh2k1e/Kconfig A src/mainboard/sony/vpceh2k1e/Kconfig.name A src/mainboard/sony/vpceh2k1e/Makefile.inc A src/mainboard/sony/vpceh2k1e/acpi/ec.asl A src/mainboard/sony/vpceh2k1e/acpi/platform.asl A src/mainboard/sony/vpceh2k1e/acpi/superio.asl A src/mainboard/sony/vpceh2k1e/acpi/thermal.asl A src/mainboard/sony/vpceh2k1e/acpi_tables.c A src/mainboard/sony/vpceh2k1e/board_info.txt A src/mainboard/sony/vpceh2k1e/devicetree.cb A src/mainboard/sony/vpceh2k1e/dsdt.asl A src/mainboard/sony/vpceh2k1e/early_init.c A src/mainboard/sony/vpceh2k1e/gpio.c A src/mainboard/sony/vpceh2k1e/hda_verb.c A src/mainboard/sony/vpceh2k1e/mainboard.c 17 files changed, 1,743 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/30973/6
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30973 )
Change subject: src/mainboard/sony: Add Sony VPCEH2K1E ......................................................................
Patch Set 6:
(10 comments)
https://review.coreboot.org/c/coreboot/+/30973/3/src/mainboard/sony/vpceh2k1... File src/mainboard/sony/vpceh2k1e/Kconfig:
https://review.coreboot.org/c/coreboot/+/30973/3/src/mainboard/sony/vpceh2k1... PS3, Line 33:
Specify Nvidia GPU's PCI ID here for the VBIOS
Done
https://review.coreboot.org/c/coreboot/+/30973/3/src/mainboard/sony/vpceh2k1... File src/mainboard/sony/vpceh2k1e/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/30973/3/src/mainboard/sony/vpceh2k1... PS3, Line 5: chip cpu/intel/socket_rPGA989 : device lapic 0x0 on : end : end
Recent patch changes this
Done
https://review.coreboot.org/c/coreboot/+/30973/3/src/mainboard/sony/vpceh2k1... File src/mainboard/sony/vpceh2k1e/dsdt.asl:
https://review.coreboot.org/c/coreboot/+/30973/3/src/mainboard/sony/vpceh2k1... PS3, Line 21: #include <arch/acpi.h>
Space afterwards
Done
https://review.coreboot.org/c/coreboot/+/30973/3/src/mainboard/sony/vpceh2k1... PS3, Line 31: /* Some generic macros */
Banish
Done
https://review.coreboot.org/c/coreboot/+/30973/3/src/mainboard/sony/vpceh2k1... File src/mainboard/sony/vpceh2k1e/mainboard.c:
https://review.coreboot.org/c/coreboot/+/30973/3/src/mainboard/sony/vpceh2k1... PS3, Line 26: remove
Banish
Done
https://review.coreboot.org/c/coreboot/+/30973/4/src/mainboard/sony/vpceh2k1... File src/mainboard/sony/vpceh2k1e/romstage.c:
https://review.coreboot.org/c/coreboot/+/30973/4/src/mainboard/sony/vpceh2k1... PS4, Line 38: 0x82
Right... […]
Ack
https://review.coreboot.org/c/coreboot/+/30973/4/src/mainboard/sony/vpceh2k1... PS4, Line 38: 0x1c01
use macros in sb/intel/bd82x6x/pch. […]
Ack
https://review.coreboot.org/c/coreboot/+/30973/4/src/mainboard/sony/vpceh2k1... PS4, Line 40: pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x000c1641);
if you don't need to access those IO ranges in the romstage you should remove it here.
Ack
https://review.coreboot.org/c/coreboot/+/30973/4/src/mainboard/sony/vpceh2k1... PS4, Line 42: 0x80
LPC_IO_DEC
Ack
https://review.coreboot.org/c/coreboot/+/30973/5/src/mainboard/sony/vpceh2k1... File src/mainboard/sony/vpceh2k1e/romstage.c:
https://review.coreboot.org/c/coreboot/+/30973/5/src/mainboard/sony/vpceh2k1... PS5, Line 17:
#include <device/pci_ops.h> […]
Ack
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30973 )
Change subject: src/mainboard/sony: Add Sony VPCEH2K1E ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/c/coreboot/+/30973/5//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/30973/5//COMMIT_MSG@21 PS5, Line 21: TODO: Use FMAP to put EC firmware in its place
Tested, required.
Ack
Hello build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/30973
to look at the new patch set (#7).
Change subject: src/mainboard/sony: Add Sony VPCEH2K1E ......................................................................
src/mainboard/sony: Add Sony VPCEH2K1E
Run autoport. It has a Nvidia graphics card and a Nuvoton NPCE795 EC. It boots fine with the VGA BIOS, EHCI debug is on the front right USB port, HDMI should work, all PCI devices are found. EC firmware is shared with the main flash chip, it is a chunk of 128KiB at the beginning of the BIOS region. The power button works, automatic fan control is working as well. Keyboard works, brightness keys do NOT work though! Touchpad works too.
EC ACPI IS NOT WORKING. HOWEVER, I THINK I FIGURED IT OUT.
Everything else is untested!
TODO: Use FMAP to put EC firmware in its place
Change-Id: Ibf324f1276611ab06d5906cab87ad538bfad7218 Signed-off-by: Angel Pons th3fanbus@gmail.com --- A src/mainboard/sony/Kconfig A src/mainboard/sony/Kconfig.name A src/mainboard/sony/vpceh2k1e/Kconfig A src/mainboard/sony/vpceh2k1e/Kconfig.name A src/mainboard/sony/vpceh2k1e/Makefile.inc A src/mainboard/sony/vpceh2k1e/acpi/ac.asl A src/mainboard/sony/vpceh2k1e/acpi/battery.asl A src/mainboard/sony/vpceh2k1e/acpi/ec.asl A src/mainboard/sony/vpceh2k1e/acpi/platform.asl A src/mainboard/sony/vpceh2k1e/acpi/snc.asl A src/mainboard/sony/vpceh2k1e/acpi/superio.asl A src/mainboard/sony/vpceh2k1e/acpi/thermal.asl A src/mainboard/sony/vpceh2k1e/acpi_tables.c A src/mainboard/sony/vpceh2k1e/board_info.txt A src/mainboard/sony/vpceh2k1e/devicetree.cb A src/mainboard/sony/vpceh2k1e/dsdt.asl A src/mainboard/sony/vpceh2k1e/early_init.c A src/mainboard/sony/vpceh2k1e/gpio.c A src/mainboard/sony/vpceh2k1e/hda_verb.c A src/mainboard/sony/vpceh2k1e/mainboard.c 20 files changed, 2,544 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/30973/7
Hello build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/30973
to look at the new patch set (#8).
Change subject: src/mainboard/sony: Add Sony VPCEH2K1E ......................................................................
src/mainboard/sony: Add Sony VPCEH2K1E
Run autoport. It has a Nvidia graphics card and a Nuvoton NPCE795 EC. It boots fine with the VGA BIOS, EHCI debug is on the front right USB port, HDMI should work, all PCI devices are found. EC firmware is shared with the main flash chip, it is a chunk of 128KiB at the beginning of the BIOS region. The power button works, automatic fan control is working as well. Keyboard works, brightness keys do NOT work though! Touchpad works too.
EC ACPI IS NOT WORKING. HOWEVER, I THINK I FIGURED IT OUT.
Everything else is untested!
TODO: Use FMAP to put EC firmware in its place
Change-Id: Ibf324f1276611ab06d5906cab87ad538bfad7218 Signed-off-by: Angel Pons th3fanbus@gmail.com --- A src/mainboard/sony/Kconfig A src/mainboard/sony/Kconfig.name A src/mainboard/sony/vpceh2k1e/Kconfig A src/mainboard/sony/vpceh2k1e/Kconfig.name A src/mainboard/sony/vpceh2k1e/Makefile.inc A src/mainboard/sony/vpceh2k1e/acpi/ac.asl A src/mainboard/sony/vpceh2k1e/acpi/battery.asl A src/mainboard/sony/vpceh2k1e/acpi/ec.asl A src/mainboard/sony/vpceh2k1e/acpi/platform.asl A src/mainboard/sony/vpceh2k1e/acpi/snc.asl A src/mainboard/sony/vpceh2k1e/acpi/superio.asl A src/mainboard/sony/vpceh2k1e/acpi/thermal.asl A src/mainboard/sony/vpceh2k1e/acpi_tables.c A src/mainboard/sony/vpceh2k1e/board_info.txt A src/mainboard/sony/vpceh2k1e/devicetree.cb A src/mainboard/sony/vpceh2k1e/dsdt.asl A src/mainboard/sony/vpceh2k1e/early_init.c A src/mainboard/sony/vpceh2k1e/gpio.c A src/mainboard/sony/vpceh2k1e/hda_verb.c A src/mainboard/sony/vpceh2k1e/mainboard.c 20 files changed, 2,361 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/30973/8
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30973 )
Change subject: src/mainboard/sony: Add Sony VPCEH2K1E ......................................................................
Patch Set 8:
(1 comment)
https://review.coreboot.org/c/coreboot/+/30973/8//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/30973/8//COMMIT_MSG@7 PS8, Line 7: src/ Remove.
Hello build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/30973
to look at the new patch set (#9).
Change subject: [WIP] mainboard/sony: Add Sony VPCEH2K1E ......................................................................
[WIP] mainboard/sony: Add Sony VPCEH2K1E
Run autoport. It has a Nvidia graphics card and a Nuvoton NPCE795 EC. It boots fine with the VGA BIOS, EHCI debug is on the front right USB port, HDMI should work, all PCI devices are found. EC firmware is shared with the main flash chip, it is a chunk of 128KiB at the beginning of the BIOS region. The power button works, automatic fan control is working as well. Keyboard works, brightness keys do NOT work though! Touchpad works too.
EC ACPI IS NOT WORKING. HOWEVER, I THINK I FIGURED IT OUT.
Everything else is untested!
TODO: Use FMAP to put EC firmware in its place
Change-Id: Ibf324f1276611ab06d5906cab87ad538bfad7218 Signed-off-by: Angel Pons th3fanbus@gmail.com --- A src/mainboard/sony/Kconfig A src/mainboard/sony/Kconfig.name A src/mainboard/sony/vpceh2k1e/Kconfig A src/mainboard/sony/vpceh2k1e/Kconfig.name A src/mainboard/sony/vpceh2k1e/Makefile.inc A src/mainboard/sony/vpceh2k1e/acpi/ac.asl A src/mainboard/sony/vpceh2k1e/acpi/battery.asl A src/mainboard/sony/vpceh2k1e/acpi/ec.asl A src/mainboard/sony/vpceh2k1e/acpi/platform.asl A src/mainboard/sony/vpceh2k1e/acpi/snc.asl A src/mainboard/sony/vpceh2k1e/acpi/superio.asl A src/mainboard/sony/vpceh2k1e/acpi/thermal.asl A src/mainboard/sony/vpceh2k1e/acpi_tables.c A src/mainboard/sony/vpceh2k1e/board_info.txt A src/mainboard/sony/vpceh2k1e/devicetree.cb A src/mainboard/sony/vpceh2k1e/dsdt.asl A src/mainboard/sony/vpceh2k1e/early_init.c A src/mainboard/sony/vpceh2k1e/gpio.c A src/mainboard/sony/vpceh2k1e/hda_verb.c A src/mainboard/sony/vpceh2k1e/mainboard.c 20 files changed, 2,361 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/30973/9
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30973 )
Change subject: [WIP] mainboard/sony: Add Sony VPCEH2K1E ......................................................................
Patch Set 9:
(1 comment)
https://review.coreboot.org/c/coreboot/+/30973/8//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/30973/8//COMMIT_MSG@7 PS8, Line 7: src/
Remove.
Done
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30973 )
Change subject: [WIP] mainboard/sony: Add Sony VPCEH2K1E ......................................................................
Patch Set 9:
(1 comment)
https://review.coreboot.org/c/coreboot/+/30973/8/src/mainboard/sony/vpceh2k1... File src/mainboard/sony/vpceh2k1e/acpi/thermal.asl:
https://review.coreboot.org/c/coreboot/+/30973/8/src/mainboard/sony/vpceh2k1... PS8, Line 146: This is wrong
Hello build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/30973
to look at the new patch set (#10).
Change subject: [WIP] mainboard/sony: Add Sony VPCEH2K1E ......................................................................
[WIP] mainboard/sony: Add Sony VPCEH2K1E
Run autoport. It has a Nvidia graphics card and a Nuvoton NPCE795 EC. It boots fine with the VGA BIOS, EHCI debug is on the front right USB port, HDMI should work, all PCI devices are found. EC firmware is shared with the main flash chip, it is a chunk of 128KiB at the beginning of the BIOS region. The power button works, automatic fan control is working as well. Keyboard works, brightness keys do NOT work though! Touchpad works too.
EC ACPI IS NOT WORKING. HOWEVER, I THINK I FIGURED IT OUT.
Everything else is untested!
TODO: Use FMAP to put EC firmware in its place
Change-Id: Ibf324f1276611ab06d5906cab87ad538bfad7218 Signed-off-by: Angel Pons th3fanbus@gmail.com --- A src/mainboard/sony/Kconfig A src/mainboard/sony/Kconfig.name A src/mainboard/sony/vpceh2k1e/Kconfig A src/mainboard/sony/vpceh2k1e/Kconfig.name A src/mainboard/sony/vpceh2k1e/Makefile.inc A src/mainboard/sony/vpceh2k1e/acpi/ac.asl A src/mainboard/sony/vpceh2k1e/acpi/battery.asl A src/mainboard/sony/vpceh2k1e/acpi/ec.asl A src/mainboard/sony/vpceh2k1e/acpi/platform.asl A src/mainboard/sony/vpceh2k1e/acpi/snc.asl A src/mainboard/sony/vpceh2k1e/acpi/superio.asl A src/mainboard/sony/vpceh2k1e/acpi_tables.c A src/mainboard/sony/vpceh2k1e/board_info.txt A src/mainboard/sony/vpceh2k1e/devicetree.cb A src/mainboard/sony/vpceh2k1e/dsdt.asl A src/mainboard/sony/vpceh2k1e/early_init.c A src/mainboard/sony/vpceh2k1e/gpio.c A src/mainboard/sony/vpceh2k1e/hda_verb.c A src/mainboard/sony/vpceh2k1e/mainboard.c 19 files changed, 2,214 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/30973/10
-
Angel Pons (Code Review) -
Arthur Heymans (Code Review)
-
build bot (Jenkins) (Code Review)
-
Paul Menzel (Code Review)