Change in coreboot[master]: soc/amd/cezanne: Add SPI registers

[Raul Rangel (Code Review)]

Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held.
Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/50445 )

Change subject: soc/amd/cezanne: Add SPI registers
......................................................................

soc/amd/cezanne: Add SPI registers

These are identical to picasso.

Signed-off-by: Raul E Rangel 
Change-Id: I3ef4c51ef6d656b3b035d97a56b1875b40e89210
---
A src/soc/amd/cezanne/include/soc/lpc.h
1 file changed, 16 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/50445/1

diff --git a/src/soc/amd/cezanne/include/soc/lpc.h b/src/soc/amd/cezanne/include/soc/lpc.h
new file mode 100644
index 0000000..fcdcd96
--- /dev/null
+++ b/src/soc/amd/cezanne/include/soc/lpc.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef AMD_CEZANNE_LPC_H
+#define AMD_CEZANNE_LPC_H
+
+#define SPIROM_BASE_ADDRESS_REGISTER	0xa0
+#define   SPI_BASE_ALIGNMENT		BIT(8)
+#define   SPI_BASE_RESERVED		(BIT(5) | BIT(6) | BIT(7))
+#define   PSP_SPI_MMIO_SEL		BIT(4)
+#define   ROUTE_TPM_2_SPI		BIT(3)
+#define   SPI_ABORT_ENABLE		BIT(2)
+#define   SPI_ROM_ENABLE		BIT(1)
+#define   SPI_ROM_ALT_ENABLE		BIT(0)
+#define   SPI_PRESERVE_BITS		(BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4))
+
+#endif /* AMD_CEZANNE_LPC_H */