Attention is currently required from: Bora Guvendik, Zhixing Ma, Anil Kumar K, Hannah Williams, Cliff Huang, Tarun Tuli, Nico Huber, Michał Żygowski, Subrata Banik, Paul Menzel, Arthur Heymans, Swift Geek (Sebastian Grzywna).
Jérémy Compostella has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70299 )
Change subject: soc/intel/common/block: Add Intel VGA early graphics support
......................................................................
Patch Set 33:
(1 comment)
File src/soc/intel/common/block/graphics/early_graphics.c:
https://review.coreboot.org/c/coreboot/+/70299/comment/b695441f_59310a19
PS23, Line 32:
: /*
: * Graphics MMIO device configuration may have been corrupted since it
: * has been initialized. The execution of a binary block such as FSP may
: * indeed have reset the PCI BAR0 address of the graphic device.
: */
: early_graphics_soc_device_init();
I performed a quick analysis of the impact on the kernel PCI enumeration and IGD resource allocation […]
I got confirmation that this should not be an issue. "the GPU and driver are able to address up to 48 bits, so should be no issues if you go above 4GB".
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