Change in coreboot[master]: soc/intel: Use config_of() - coreboot-gerrit

14 Jul 2019

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34328 )
Change subject: soc/intel: Use config_of()
......................................................................
soc/intel: Use config_of()
Change-Id: I0727a6b327410197cf32f598d1312737744386b3
Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com
---
M src/soc/intel/apollolake/lpc.c
M src/soc/intel/apollolake/memmap.c
M src/soc/intel/apollolake/pmc.c
M src/soc/intel/apollolake/romstage.c
M src/soc/intel/apollolake/sd.c
M src/soc/intel/baytrail/ehci.c
M src/soc/intel/baytrail/emmc.c
M src/soc/intel/baytrail/gfx.c
M src/soc/intel/baytrail/lpe.c
M src/soc/intel/baytrail/lpss.c
M src/soc/intel/baytrail/pcie.c
M src/soc/intel/baytrail/romstage/pmc.c
M src/soc/intel/baytrail/sata.c
M src/soc/intel/baytrail/sd.c
M src/soc/intel/baytrail/southcluster.c
M src/soc/intel/baytrail/xhci.c
M src/soc/intel/braswell/chip.c
M src/soc/intel/braswell/emmc.c
M src/soc/intel/braswell/lpe.c
M src/soc/intel/braswell/lpss.c
M src/soc/intel/braswell/pcie.c
M src/soc/intel/braswell/romstage/romstage.c
M src/soc/intel/braswell/sd.c
M src/soc/intel/braswell/southcluster.c
M src/soc/intel/braswell/xhci.c
M src/soc/intel/broadwell/adsp.c
M src/soc/intel/broadwell/igd.c
M src/soc/intel/broadwell/lpc.c
M src/soc/intel/broadwell/me.c
M src/soc/intel/broadwell/pcie.c
M src/soc/intel/broadwell/romstage/pch.c
M src/soc/intel/broadwell/sata.c
M src/soc/intel/broadwell/serialio.c
M src/soc/intel/cannonlake/lpc.c
M src/soc/intel/cannonlake/memmap.c
M src/soc/intel/cannonlake/pmutil.c
M src/soc/intel/cannonlake/romstage/fsp_params.c
M src/soc/intel/cannonlake/sd.c
M src/soc/intel/cannonlake/smihandler.c
M src/soc/intel/common/block/lpc/lpc_lib.c
M src/soc/intel/denverton_ns/lpc.c
M src/soc/intel/denverton_ns/sata.c
M src/soc/intel/fsp_baytrail/acpi.c
M src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c
M src/soc/intel/fsp_baytrail/lpe.c
M src/soc/intel/fsp_baytrail/lpss.c
M src/soc/intel/fsp_broadwell_de/iou_complto.c
M src/soc/intel/icelake/espi.c
M src/soc/intel/icelake/memmap.c
M src/soc/intel/icelake/pmutil.c
M src/soc/intel/icelake/romstage/fsp_params.c
M src/soc/intel/icelake/sd.c
M src/soc/intel/icelake/smihandler.c
M src/soc/intel/quark/romstage/fsp2_0.c
M src/soc/intel/skylake/chip.c
M src/soc/intel/skylake/finalize.c
M src/soc/intel/skylake/graphics.c
M src/soc/intel/skylake/irq.c
M src/soc/intel/skylake/lpc.c
M src/soc/intel/skylake/memmap.c
M src/soc/intel/skylake/pmutil.c
M src/soc/intel/skylake/romstage/romstage.c
M src/soc/intel/skylake/romstage/romstage_fsp20.c
M src/soc/intel/skylake/sd.c
M src/soc/intel/skylake/systemagent.c
M src/soc/intel/skylake/thermal.c
66 files changed, 100 insertions(+), 179 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/34328/1

diff --git a/src/soc/intel/apollolake/lpc.c b/src/soc/intel/apollolake/lpc.c
index ceed8f2..2d59f7d 100644
--- a/src/soc/intel/apollolake/lpc.c
+++ b/src/soc/intel/apollolake/lpc.c
@@ -91,12 +91,7 @@
 void lpc_soc_init(struct device *dev)
 {
    const struct soc_intel_apollolake_config *cfg;
-
-	cfg = dev->chip_info;
-	if (!cfg) {
-		printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n");
-		return;
-	}
+	cfg = config_of(dev);
/* Set LPC Serial IRQ mode */
    lpc_set_serirq_mode(cfg->serirq_mode);
diff --git a/src/soc/intel/apollolake/memmap.c b/src/soc/intel/apollolake/memmap.c
index 3436364..66f4dda 100644
--- a/src/soc/intel/apollolake/memmap.c
+++ b/src/soc/intel/apollolake/memmap.c
@@ -28,20 +28,13 @@
void *cbmem_top(void)
 {
-	const struct device *dev;
    const config_t *config;
    void *tolum = (void *)sa_get_tseg_base();
if (!CONFIG(SOC_INTEL_GLK))
    	return tolum;
-	dev = pcidev_path_on_root(PCH_DEVFN_LPC);
-	assert(dev != NULL);
-	config = dev->chip_info;
-
-	if (!config)
-		die_with_post_code(POST_HW_INIT_FAILURE,
-			"Failed to get chip_info\n");
+	config = config_of_path(PCH_DEVFN_LPC);
/* FSP allocates 2x PRMRR Size Memory for alignment */
    if (config->sgx_enable)
diff --git a/src/soc/intel/apollolake/pmc.c b/src/soc/intel/apollolake/pmc.c
index 0400a9d..33fc457 100644
--- a/src/soc/intel/apollolake/pmc.c
+++ b/src/soc/intel/apollolake/pmc.c
@@ -94,7 +94,7 @@
void pmc_soc_init(struct device *dev)
 {
-	const struct soc_intel_apollolake_config *cfg = dev->chip_info;
+	const struct soc_intel_apollolake_config *cfg = config_of(dev);
/* Set up GPE configuration */
    pmc_gpe_init();
diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c
index 6d3b346..7b10222 100644
--- a/src/soc/intel/apollolake/romstage.c
+++ b/src/soc/intel/apollolake/romstage.c
@@ -311,13 +311,9 @@
 {
 #if CONFIG(SOC_INTEL_GLK)
    /* Only for GLK */
-	const struct device *dev = pcidev_path_on_root(PCH_DEVFN_LPC);
-	assert(dev != NULL);
-	const config_t *config = dev->chip_info;
    FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;
-	if (!config)
-		die("Can not find SoC devicetree\n");
+	const config_t *config = config_of_path(PCH_DEVFN_LPC);
m_cfg->PrmrrSize = config->PrmrrSize;
diff --git a/src/soc/intel/apollolake/sd.c b/src/soc/intel/apollolake/sd.c
index 35db804..e34d53e 100644
--- a/src/soc/intel/apollolake/sd.c
+++ b/src/soc/intel/apollolake/sd.c
@@ -18,7 +18,7 @@
int sd_fill_soc_gpio_info(struct acpi_gpio* gpio, struct device *dev)
 {
-	config_t *config = dev->chip_info;
+	config_t *config = config_of(dev);
if (!config->sdcard_cd_gpio)
    	return -1;
diff --git a/src/soc/intel/baytrail/ehci.c b/src/soc/intel/baytrail/ehci.c
index 002d38c..9082fea 100644
--- a/src/soc/intel/baytrail/ehci.c
+++ b/src/soc/intel/baytrail/ehci.c
@@ -88,7 +88,7 @@
static void usb2_phy_init(struct device *dev)
 {
-	struct soc_intel_baytrail_config *config = dev->chip_info;
+	struct soc_intel_baytrail_config *config = config_of(dev);
    u32 usb2_comp_bg = (config->usb2_comp_bg == 0 ?
    		    0x4700 : config->usb2_comp_bg);
    struct reg_script usb2_phy_script[] = {
@@ -123,7 +123,7 @@
static void ehci_init(struct device *dev)
 {
-	struct soc_intel_baytrail_config *config = dev->chip_info;
+	struct soc_intel_baytrail_config *config = config_of(dev);
    struct reg_script ehci_hc_init[] = {
    	/* Controller init */
    	REG_SCRIPT_NEXT(ehci_init_script),
diff --git a/src/soc/intel/baytrail/emmc.c b/src/soc/intel/baytrail/emmc.c
index bf5a8dd..a99fe5a 100644
--- a/src/soc/intel/baytrail/emmc.c
+++ b/src/soc/intel/baytrail/emmc.c
@@ -46,7 +46,7 @@
static void emmc_init(struct device *dev)
 {
-	struct soc_intel_baytrail_config *config = dev->chip_info;
+	struct soc_intel_baytrail_config *config = config_of(dev);
printk(BIOS_DEBUG, "eMMC init\n");
    reg_script_run_on_dev(dev, emmc_ops);
diff --git a/src/soc/intel/baytrail/gfx.c b/src/soc/intel/baytrail/gfx.c
index 2048c13..4a79991 100644
--- a/src/soc/intel/baytrail/gfx.c
+++ b/src/soc/intel/baytrail/gfx.c
@@ -313,7 +313,7 @@
static void gfx_panel_setup(struct device *dev)
 {
-	struct soc_intel_baytrail_config *config = dev->chip_info;
+	struct soc_intel_baytrail_config *config = config_of(dev);
    struct reg_script gfx_pipea_init[] = {
    	/* CONTROL */
    	REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEA_REG(PP_CONTROL),
diff --git a/src/soc/intel/baytrail/lpe.c b/src/soc/intel/baytrail/lpe.c
index 1843f08..9636640 100644
--- a/src/soc/intel/baytrail/lpe.c
+++ b/src/soc/intel/baytrail/lpe.c
@@ -91,7 +91,7 @@
    struct soc_intel_baytrail_config *config;
    const char *freq_str;
-	config = dev->chip_info;
+	config = config_of(dev);
    switch (config->lpe_codec_clk_freq) {
    case 19:
    	freq_str = "19.2";
@@ -150,7 +150,7 @@
static void lpe_init(struct device *dev)
 {
-	struct soc_intel_baytrail_config *config = dev->chip_info;
+	struct soc_intel_baytrail_config *config = config_of(dev);
lpe_stash_firmware_info(dev);
diff --git a/src/soc/intel/baytrail/lpss.c b/src/soc/intel/baytrail/lpss.c
index a21a788..4ffdca9 100644
--- a/src/soc/intel/baytrail/lpss.c
+++ b/src/soc/intel/baytrail/lpss.c
@@ -148,7 +148,7 @@
static void lpss_init(struct device *dev)
 {
-	struct soc_intel_baytrail_config *config = dev->chip_info;
+	struct soc_intel_baytrail_config *config = config_of(dev);
    int iosf_reg, nvs_index;
dev_ctl_reg(dev, &iosf_reg, &nvs_index);
diff --git a/src/soc/intel/baytrail/pcie.c b/src/soc/intel/baytrail/pcie.c
index 33c5455..b2b2d3c 100644
--- a/src/soc/intel/baytrail/pcie.c
+++ b/src/soc/intel/baytrail/pcie.c
@@ -108,11 +108,11 @@
    reg_script_run_on_dev(dev, init_script);
if (is_first_port(dev)) {
-		struct soc_intel_baytrail_config *config = dev->chip_info;
+		struct soc_intel_baytrail_config *config = config_of(dev);
    	uint32_t reg = pci_read_config32(dev, RPPGEN);
    	reg |= SRDLCGEN | SRDBCGEN;
-		if (config && config->clkreq_enable)
+		if (config->clkreq_enable)
    		reg |= LCLKREQEN | BBCLKREQEN;
pci_write_config32(dev, RPPGEN, reg);
@@ -208,13 +208,13 @@
 static void byt_pcie_enable(struct device *dev)
 {
    if (is_first_port(dev)) {
-		struct soc_intel_baytrail_config *config = dev->chip_info;
+		struct soc_intel_baytrail_config *config = config_of(dev);
    	uint32_t reg = pci_read_config32(dev, PHYCTL2_IOSFBCTL);
    	pll_en_off = !!(reg & PLL_OFF_EN);
strpfusecfg = pci_read_config32(dev, STRPFUSECFG);
-		if (config && config->pcie_wake_enable)
+		if (config->pcie_wake_enable)
    		southcluster_smm_save_param(
    			SMM_SAVE_PARAM_PCIE_WAKE_ENABLE, 1);
    }
diff --git a/src/soc/intel/baytrail/romstage/pmc.c b/src/soc/intel/baytrail/romstage/pmc.c
index 596ed11..a3f8c4a 100644
--- a/src/soc/intel/baytrail/romstage/pmc.c
+++ b/src/soc/intel/baytrail/romstage/pmc.c
@@ -48,7 +48,7 @@
    dev = pcidev_on_root(SOC_DEV, SOC_FUNC);
if (dev)
-		cfg = dev->chip_info;
+		cfg = config_of(dev);
reg = iosf_punit_read(SB_BIOS_CONFIG);
    /* Write bits 17:16 of SB_BIOS_CONFIG in the PUNIT. */
diff --git a/src/soc/intel/baytrail/sata.c b/src/soc/intel/baytrail/sata.c
index e7636fe..084d786 100644
--- a/src/soc/intel/baytrail/sata.c
+++ b/src/soc/intel/baytrail/sata.c
@@ -36,18 +36,13 @@
static void sata_init(struct device *dev)
 {
-	config_t *config = dev->chip_info;
+	config_t *config = config_of(dev);
    u32 reg32;
    u16 reg16;
    u8  reg8;
printk(BIOS_DEBUG, "SATA: Initializing...\n");
-	if (config == NULL) {
-		printk(BIOS_ERR, "SATA: ERROR: Device not in devicetree.cb!\n");
-		return;
-	}
-
    if (!config->sata_ahci) {
    	/* Set legacy or native decoding mode */
    	if (config->ide_legacy_combined) {
@@ -158,14 +153,12 @@
static void sata_enable(struct device *dev)
 {
-	config_t *config = dev->chip_info;
+	config_t *config = config_of(dev);
    u8  reg8;
    u16 reg16;
    u32 reg32;
southcluster_enable_dev(dev);
-	if (!config)
-		return;
/* Port mapping -- mask off SPD + SMS + SC bits, then re-set */
    reg16 = pci_read_config16(dev, 0x90);
diff --git a/src/soc/intel/baytrail/sd.c b/src/soc/intel/baytrail/sd.c
index cbdb7bb..dcb2073 100644
--- a/src/soc/intel/baytrail/sd.c
+++ b/src/soc/intel/baytrail/sd.c
@@ -32,10 +32,7 @@
static void sd_init(struct device *dev)
 {
-	struct soc_intel_baytrail_config *config = dev->chip_info;
-
-	if (config == NULL)
-		return;
+	struct soc_intel_baytrail_config *config = config_of(dev);
if (config->sdcard_cap_low != 0 || config->sdcard_cap_high != 0) {
    	printk(BIOS_DEBUG, "Overriding SD Card controller caps.\n");
diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c
index 0289e8b..8f65433 100644
--- a/src/soc/intel/baytrail/southcluster.c
+++ b/src/soc/intel/baytrail/southcluster.c
@@ -177,7 +177,7 @@
    u32 *gen_pmcon1 = (u32 *)(PMC_BASE_ADDRESS + GEN_PMCON1);
    u32 *actl = (u32 *)(ILB_BASE_ADDRESS + ACTL);
    const struct baytrail_irq_route *ir = &global_baytrail_irq_route;
-	struct soc_intel_baytrail_config *config = dev->chip_info;
+	struct soc_intel_baytrail_config *config = config_of(dev);
/* Set up the PIRQ PIC routing based on static config. */
    for (i = 0; i < NUM_PIRQS; i++) {
diff --git a/src/soc/intel/baytrail/xhci.c b/src/soc/intel/baytrail/xhci.c
index 6408cd9..d9f2c53 100644
--- a/src/soc/intel/baytrail/xhci.c
+++ b/src/soc/intel/baytrail/xhci.c
@@ -197,7 +197,7 @@
static void xhci_init(struct device *dev)
 {
-	struct soc_intel_baytrail_config *config = dev->chip_info;
+	struct soc_intel_baytrail_config *config = config_of(dev);
    struct reg_script xhci_hc_init[] = {
    	/* Initialize clock gating */
    	REG_SCRIPT_NEXT(xhci_clock_gating_script),
diff --git a/src/soc/intel/braswell/chip.c b/src/soc/intel/braswell/chip.c
index 900b2f3..d179cea 100644
--- a/src/soc/intel/braswell/chip.c
+++ b/src/soc/intel/braswell/chip.c
@@ -96,7 +96,7 @@
    	return;
    }
-	config = dev->chip_info;
+	config = config_of(dev);
/* Set the parameters for SiliconInit */
    printk(BIOS_DEBUG, "Updating UPD values for SiliconInit\n");
diff --git a/src/soc/intel/braswell/emmc.c b/src/soc/intel/braswell/emmc.c
index 09e801d..aae496a 100644
--- a/src/soc/intel/braswell/emmc.c
+++ b/src/soc/intel/braswell/emmc.c
@@ -33,7 +33,7 @@
static void emmc_init(struct device *dev)
 {
-	struct soc_intel_braswell_config *config = dev->chip_info;
+	struct soc_intel_braswell_config *config = config_of(dev);
printk(BIOS_SPEW, "%s/%s (%s)\n",
    		__FILE__, __func__, dev_name(dev));
diff --git a/src/soc/intel/braswell/lpe.c b/src/soc/intel/braswell/lpe.c
index a06d7a6..58e3492 100644
--- a/src/soc/intel/braswell/lpe.c
+++ b/src/soc/intel/braswell/lpe.c
@@ -96,7 +96,7 @@
    struct soc_intel_braswell_config *config;
    const char *freq_str;
-	config = dev->chip_info;
+	config = config_of(dev);
    switch (config->lpe_codec_clk_src) {
    case LPE_CLK_SRC_XTAL:
    	/* XTAL driven bit2=0 */
@@ -152,7 +152,7 @@
static void lpe_init(struct device *dev)
 {
-	struct soc_intel_braswell_config *config = dev->chip_info;
+	struct soc_intel_braswell_config *config = config_of(dev);
printk(BIOS_SPEW, "%s/%s (%s)\n",
    		__FILE__, __func__, dev_name(dev));
diff --git a/src/soc/intel/braswell/lpss.c b/src/soc/intel/braswell/lpss.c
index d1ce76a..245fc4f 100644
--- a/src/soc/intel/braswell/lpss.c
+++ b/src/soc/intel/braswell/lpss.c
@@ -139,7 +139,7 @@
static void lpss_init(struct device *dev)
 {
-	struct soc_intel_braswell_config *config = dev->chip_info;
+	struct soc_intel_braswell_config *config = config_of(dev);
    int iosf_reg, nvs_index;
printk(BIOS_SPEW, "%s/%s (%s)\n",
diff --git a/src/soc/intel/braswell/pcie.c b/src/soc/intel/braswell/pcie.c
index 6e387d1..dc779bb 100644
--- a/src/soc/intel/braswell/pcie.c
+++ b/src/soc/intel/braswell/pcie.c
@@ -141,13 +141,13 @@
    printk(BIOS_SPEW, "%s/%s (%s)\n",
    		__FILE__, __func__, dev_name(dev));
    if (is_first_port(dev)) {
-		struct soc_intel_braswell_config *config = dev->chip_info;
+		struct soc_intel_braswell_config *config = config_of(dev);
    	uint32_t reg = pci_read_config32(dev, PHYCTL2_IOSFBCTL);
    	pll_en_off = !!(reg & PLL_OFF_EN);
strpfusecfg = pci_read_config32(dev, STRPFUSECFG);
-		if (config && config->pcie_wake_enable)
+		if (config->pcie_wake_enable)
    		southcluster_smm_save_param(
    			SMM_SAVE_PARAM_PCIE_WAKE_ENABLE, 1);
    }
diff --git a/src/soc/intel/braswell/romstage/romstage.c b/src/soc/intel/braswell/romstage/romstage.c
index e0e22f2..38a0c2e 100644
--- a/src/soc/intel/braswell/romstage/romstage.c
+++ b/src/soc/intel/braswell/romstage/romstage.c
@@ -124,7 +124,7 @@
    	return;
    }
-	config = dev->chip_info;
+	config = config_of(dev);
    printk(BIOS_DEBUG, "Updating UPD values for MemoryInit\n");
    upd->PcdMrcInitTsegSize = CONFIG(HAVE_SMI_HANDLER) ?
    	config->PcdMrcInitTsegSize : 0;
diff --git a/src/soc/intel/braswell/sd.c b/src/soc/intel/braswell/sd.c
index 2f3dadb..3816fc4 100644
--- a/src/soc/intel/braswell/sd.c
+++ b/src/soc/intel/braswell/sd.c
@@ -33,14 +33,11 @@
static void sd_init(struct device *dev)
 {
-	struct soc_intel_braswell_config *config = dev->chip_info;
+	struct soc_intel_braswell_config *config = config_of(dev);
printk(BIOS_SPEW, "%s/%s (%s)\n",
    		__FILE__, __func__, dev_name(dev));
-	if (config == NULL)
-		return;
-
    if (config->sdcard_cap_low != 0 || config->sdcard_cap_high != 0) {
    	printk(BIOS_DEBUG, "Overriding SD Card controller caps.\n");
    	pci_write_config32(dev, CAP_OVERRIDE_LOW,
diff --git a/src/soc/intel/braswell/southcluster.c b/src/soc/intel/braswell/southcluster.c
index bf9f689..67e941c 100644
--- a/src/soc/intel/braswell/southcluster.c
+++ b/src/soc/intel/braswell/southcluster.c
@@ -286,7 +286,7 @@
    const unsigned long ilb_base = ILB_BASE_ADDRESS;
    void *gen_pmcon1 = (void *)(PMC_BASE_ADDRESS + GEN_PMCON1);
    const struct soc_irq_route *ir = &global_soc_irq_route;
-	struct soc_intel_braswell_config *config = dev->chip_info;
+	struct soc_intel_braswell_config *config = config_of(dev);
printk(BIOS_SPEW, "%s/%s (%s)\n",
    		__FILE__, __func__, dev_name(dev));
diff --git a/src/soc/intel/braswell/xhci.c b/src/soc/intel/braswell/xhci.c
index 6c90482..42288f9 100644
--- a/src/soc/intel/braswell/xhci.c
+++ b/src/soc/intel/braswell/xhci.c
@@ -33,9 +33,9 @@
static void xhci_init(struct device *dev)
 {
-	struct soc_intel_braswell_config *config = dev->chip_info;
+	struct soc_intel_braswell_config *config = config_of(dev);
-	if (config && config->usb_comp_bg) {
+	if (config->usb_comp_bg) {
    	struct reg_script ops[] = {
    		REG_IOSF_WRITE(IOSF_PORT_USBPHY, USBPHY_COMPBG,
    			config->usb_comp_bg),
diff --git a/src/soc/intel/broadwell/adsp.c b/src/soc/intel/broadwell/adsp.c
index 7658515..c4023cc 100644
--- a/src/soc/intel/broadwell/adsp.c
+++ b/src/soc/intel/broadwell/adsp.c
@@ -31,7 +31,7 @@
static void adsp_init(struct device *dev)
 {
-	config_t *config = dev->chip_info;
+	config_t *config = config_of(dev);
    struct resource *bar0, *bar1;
    u32 tmp32;
diff --git a/src/soc/intel/broadwell/igd.c b/src/soc/intel/broadwell/igd.c
index 9107b23..dab2d15 100644
--- a/src/soc/intel/broadwell/igd.c
+++ b/src/soc/intel/broadwell/igd.c
@@ -298,7 +298,7 @@
static void igd_setup_panel(struct device *dev)
 {
-	config_t *conf = dev->chip_info;
+	config_t *conf = config_of(dev);
    u32 reg32;
/* Setup Digital Port Hotplug */
@@ -349,7 +349,7 @@
 static int igd_get_cdclk_haswell(u32 *const cdsel, int *const inform_pc,
    			 struct device *const dev)
 {
-	const config_t *const conf = dev->chip_info;
+	const config_t *const conf = config_of(dev);
    int cdclk = conf->cdclk;
/* Check for ULX GT1 or GT2 */
@@ -383,7 +383,7 @@
    			   struct device *const dev)
 {
    static const u32 cdsel_by_cdclk[] = { 0, 2, 0, 1, 3 };
-	const config_t *const conf = dev->chip_info;
+	const config_t *const conf = config_of(dev);
    int cdclk = conf->cdclk;
/* Check for ULX */
diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c
index 7679724..2f089dd 100644
--- a/src/soc/intel/broadwell/lpc.c
+++ b/src/soc/intel/broadwell/lpc.c
@@ -104,7 +104,7 @@
 static void pch_pirq_init(struct device *dev)
 {
    struct device *irq_dev;
-	config_t *config = dev->chip_info;
+	config_t *config = config_of(dev);
pci_write_config8(dev, PIRQA_ROUT, config->pirqa_routing);
    pci_write_config8(dev, PIRQB_ROUT, config->pirqb_routing);
@@ -151,7 +151,7 @@
    u16 reg16;
    const char *state;
    /* Get the chip configuration */
-	config_t *config = dev->chip_info;
+	config_t *config = config_of(dev);
    int pwr_on = CONFIG_MAINBOARD_POWER_FAILURE_STATE;
/* Which state do we want to goto after g3 (power restored)?
@@ -318,7 +318,7 @@
static void pch_init_deep_sx(struct device *dev)
 {
-	config_t *config = dev->chip_info;
+	config_t *config = config_of(dev);
if (config->deep_sx_enable_ac) {
    	RCBA32_OR(DEEP_S3_POL, DEEP_S3_EN_AC);
@@ -552,7 +552,7 @@
 static void pch_lpc_add_io_resources(struct device *dev)
 {
    struct resource *res;
-	config_t *config = dev->chip_info;
+	config_t *config = config_of(dev);
/* Add the default claimed IO range for the LPC device. */
    res = new_resource(dev, 0);
diff --git a/src/soc/intel/broadwell/me.c b/src/soc/intel/broadwell/me.c
index dd5e5b8..6be1748 100644
--- a/src/soc/intel/broadwell/me.c
+++ b/src/soc/intel/broadwell/me.c
@@ -971,7 +971,7 @@
 /* Check whether ME is present and do basic init */
 static void intel_me_init(struct device *dev)
 {
-	config_t *config = dev->chip_info;
+	config_t *config = config_of(dev);
    me_bios_path path = intel_me_path(dev);
    me_bios_payload mbp_data;
    int mbp_ret;
@@ -1004,7 +1004,7 @@
    intel_me_print_mbp(&mbp_data);
/* Set clock enables according to devicetree */
-	if (config && config->icc_clock_disable)
+	if (config->icc_clock_disable)
    	me_icc_set_clock_enables(config->icc_clock_disable);
/* Make sure ME is in a mode that expects EOP */
diff --git a/src/soc/intel/broadwell/pcie.c b/src/soc/intel/broadwell/pcie.c
index dff4f81..bdaced2 100644
--- a/src/soc/intel/broadwell/pcie.c
+++ b/src/soc/intel/broadwell/pcie.c
@@ -135,10 +135,8 @@
    	root_port_config_update_gbe_port();
pci_update_config8(dev, 0xe2, ~(3 << 4), (3 << 4));
-		if (dev->chip_info != NULL) {
-			config_t *config = dev->chip_info;
-			rpc.coalesce = config->pcie_port_coalesce;
-		}
+		config_t *config = config_of(dev);
+		rpc.coalesce = config->pcie_port_coalesce;
    }
rp = root_port_number(dev);
@@ -449,7 +447,7 @@
static void pch_pcie_early(struct device *dev)
 {
-	config_t *config = dev->chip_info;
+	config_t *config = config_of(dev);
    int do_aspm = 0;
    int rp = root_port_number(dev);
@@ -481,7 +479,7 @@
    }
/* Allow ASPM to be forced on in devicetree */
-	if (config && (config->pcie_port_force_aspm & (1 << (rp - 1))))
+	if ((config->pcie_port_force_aspm & (1 << (rp - 1))))
    	do_aspm = 1;
printk(BIOS_DEBUG, "PCIe Root Port %d ASPM is %sabled\n",
diff --git a/src/soc/intel/broadwell/romstage/pch.c b/src/soc/intel/broadwell/romstage/pch.c
index ea2726b..0bd4ccd 100644
--- a/src/soc/intel/broadwell/romstage/pch.c
+++ b/src/soc/intel/broadwell/romstage/pch.c
@@ -76,13 +76,9 @@
 static void pch_enable_lpc(void)
 {
    /* Lookup device tree in romstage */
-	const struct device *dev;
    const config_t *config;
-	dev = pcidev_on_root(PCH_DEV_SLOT_LPC, 0);
-	if (!dev || !dev->chip_info)
-		return;
-	config = dev->chip_info;
+	config = config_of_path(PCH_DEVFN_LPC);
pci_write_config32(PCH_DEV_LPC, LPC_GEN1_DEC, config->gen1_dec);
    pci_write_config32(PCH_DEV_LPC, LPC_GEN2_DEC, config->gen2_dec);
diff --git a/src/soc/intel/broadwell/sata.c b/src/soc/intel/broadwell/sata.c
index cb08ae7..e47a78d 100644
--- a/src/soc/intel/broadwell/sata.c
+++ b/src/soc/intel/broadwell/sata.c
@@ -41,7 +41,7 @@
static void sata_init(struct device *dev)
 {
-	config_t *config = dev->chip_info;
+	config_t *config = config_of(dev);
    u32 reg32;
    u8 *abar;
    u16 reg16;
@@ -271,7 +271,7 @@
 static void sata_enable(struct device *dev)
 {
    /* Get the chip configuration */
-	config_t *config = dev->chip_info;
+	config_t *config = config_of(dev);
    u16 map = 0x0060;
map |= (config->sata_port_map ^ 0xf) << 8;
diff --git a/src/soc/intel/broadwell/serialio.c b/src/soc/intel/broadwell/serialio.c
index 12e458c..161c875 100644
--- a/src/soc/intel/broadwell/serialio.c
+++ b/src/soc/intel/broadwell/serialio.c
@@ -170,7 +170,7 @@
static void serialio_init(struct device *dev)
 {
-	config_t *config = dev->chip_info;
+	config_t *config = config_of(dev);
    struct resource *bar0, *bar1;
    int sio_index = -1;
    u32 reg32;
diff --git a/src/soc/intel/cannonlake/lpc.c b/src/soc/intel/cannonlake/lpc.c
index 1fe0416..a7fcd94 100644
--- a/src/soc/intel/cannonlake/lpc.c
+++ b/src/soc/intel/cannonlake/lpc.c
@@ -51,7 +51,7 @@
void soc_get_gen_io_dec_range(const struct device *dev, uint32_t *gen_io_dec)
 {
-	const config_t *config = dev->chip_info;
+	const config_t *config = config_of(dev);
gen_io_dec[0] = config->gen1_dec;
    gen_io_dec[1] = config->gen2_dec;
diff --git a/src/soc/intel/cannonlake/memmap.c b/src/soc/intel/cannonlake/memmap.c
index 355c36b..18ddeee 100644
--- a/src/soc/intel/cannonlake/memmap.c
+++ b/src/soc/intel/cannonlake/memmap.c
@@ -168,7 +168,7 @@
    size_t reserve_mem_size;
    const struct soc_intel_cannonlake_config *config;
-	config = dev->chip_info;
+	config = config_of(dev);
/* Get PRMRR size */
    reserve_mem_base -= get_prmrr_size(reserve_mem_base, config);
diff --git a/src/soc/intel/cannonlake/pmutil.c b/src/soc/intel/cannonlake/pmutil.c
index 9997d16..371b52a 100644
--- a/src/soc/intel/cannonlake/pmutil.c
+++ b/src/soc/intel/cannonlake/pmutil.c
@@ -175,14 +175,7 @@
 void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2)
 {
    DEVTREE_CONST struct soc_intel_cannonlake_config *config;
-
-	/* Look up the device in devicetree */
-	DEVTREE_CONST struct device *dev = pcidev_path_on_root(PCH_DEVFN_PMC);
-	if (!dev || !dev->chip_info) {
-		printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n");
-		return;
-	}
-	config = dev->chip_info;
+	config = config_of_path(PCH_DEVFN_PMC);
/* Assign to out variable */
    *dw0 = config->gpe0_dw0;
diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c
index eb71f5d..3ba997d 100644
--- a/src/soc/intel/cannonlake/romstage/fsp_params.c
+++ b/src/soc/intel/cannonlake/romstage/fsp_params.c
@@ -103,7 +103,7 @@
    const struct device *dev = pcidev_path_on_root(PCH_DEVFN_LPC);
    const struct device *smbus = pcidev_path_on_root(PCH_DEVFN_SMBUS);
    assert(dev != NULL);
-	const config_t *config = dev->chip_info;
+	const config_t *config = config_of(dev);
    FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;
    FSP_M_TEST_CONFIG *tconfig = &mupd->FspmTestConfig;
diff --git a/src/soc/intel/cannonlake/sd.c b/src/soc/intel/cannonlake/sd.c
index 2c0298f..b69cd1a 100644
--- a/src/soc/intel/cannonlake/sd.c
+++ b/src/soc/intel/cannonlake/sd.c
@@ -18,7 +18,7 @@
int sd_fill_soc_gpio_info(struct acpi_gpio* gpio, struct device *dev)
 {
-	config_t *config = dev->chip_info;
+	config_t *config = config_of(dev);
if (!config->sdcard_cd_gpio)
    	return -1;
diff --git a/src/soc/intel/cannonlake/smihandler.c b/src/soc/intel/cannonlake/smihandler.c
index cc5a7dd..b8ceec0 100644
--- a/src/soc/intel/cannonlake/smihandler.c
+++ b/src/soc/intel/cannonlake/smihandler.c
@@ -78,15 +78,8 @@
 void smihandler_soc_at_finalize(void)
 {
    const struct soc_intel_cannonlake_config *config;
-	const struct device *dev = pcidev_path_on_root(PCH_DEVFN_CSE);
-	if (!dev || !dev->chip_info) {
-		printk(BIOS_ERR, "%s: Could not find SoC devicetree config!\n",
-		       __func__);
-		return ;
-	}
-
-	config = dev->chip_info;
+	config = config_of_path(PCH_DEVFN_CSE);
if (!config->HeciEnabled && CONFIG(HECI_DISABLE_USING_SMM))
    	pch_disable_heci();
diff --git a/src/soc/intel/common/block/lpc/lpc_lib.c b/src/soc/intel/common/block/lpc/lpc_lib.c
index 975e430..bc89e4c 100644
--- a/src/soc/intel/common/block/lpc/lpc_lib.c
+++ b/src/soc/intel/common/block/lpc/lpc_lib.c
@@ -270,7 +270,7 @@
    const struct device *dev;
dev = pcidev_on_root(PCH_DEV_SLOT_LPC, 0);
-	if (!dev || !dev->chip_info)
+	if (!dev)
    	return;
soc_pch_pirq_init(dev);
@@ -283,7 +283,7 @@
    uint32_t gen_io_dec[LPC_NUM_GENERIC_IO_RANGES];
dev = pcidev_on_root(PCH_DEV_SLOT_LPC, 0);
-	if (!dev || !dev->chip_info)
+	if (!dev)
    	return;
soc_get_gen_io_dec_range(dev, gen_io_dec);
diff --git a/src/soc/intel/denverton_ns/lpc.c b/src/soc/intel/denverton_ns/lpc.c
index 25d7c9d..5af0781 100644
--- a/src/soc/intel/denverton_ns/lpc.c
+++ b/src/soc/intel/denverton_ns/lpc.c
@@ -90,7 +90,7 @@
 {
    struct device *irq_dev;
    /* Get the chip configuration */
-	config_t *config = dev->chip_info;
+	config_t *config = config_of(dev);
/* Initialize PIRQ Routings */
    write8((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIRQA_ROUT),
diff --git a/src/soc/intel/denverton_ns/sata.c b/src/soc/intel/denverton_ns/sata.c
index ad62e51..4ea613f 100644
--- a/src/soc/intel/denverton_ns/sata.c
+++ b/src/soc/intel/denverton_ns/sata.c
@@ -35,15 +35,10 @@
    u32 abar;
/* Get the chip configuration */
-	config_t *config = dev->chip_info;
+	config_t *config = config_of(dev);
printk(BIOS_DEBUG, "SATA: Initializing...\n");
-	if (config == NULL) {
-		printk(BIOS_ERR, "SATA: ERROR: Device not in devicetree.cb!\n");
-		return;
-	}
-
    /* SATA configuration is handled by the FSP */
/* Enable BARs */
diff --git a/src/soc/intel/fsp_baytrail/acpi.c b/src/soc/intel/fsp_baytrail/acpi.c
index 371581b..fb941ab 100644
--- a/src/soc/intel/fsp_baytrail/acpi.c
+++ b/src/soc/intel/fsp_baytrail/acpi.c
@@ -177,7 +177,7 @@
    acpi_header_t *header = &(fadt->header);
    struct device *lpcdev = pcidev_path_on_root(FADT_SOC_LPC_DEVFN);
    u16 pmbase = pci_read_config16(lpcdev, ABASE) & 0xfff0;
-	config_t *config = lpcdev->chip_info;
+	config_t *config = config_of(lpcdev);
memset((void *) fadt, 0, sizeof(acpi_fadt_t));
diff --git a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c
index 7e90142..f11b206 100644
--- a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c
+++ b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c
@@ -87,7 +87,7 @@
    printk(FSP_INFO_LEVEL, "Configure Default UPD Data\n");
dev = pcidev_path_on_root(SOC_DEV_FUNC);
-	config = dev->chip_info;
+	config = config_of(dev);
/* Set up default verb tables - Just HDMI audio */
    UpdData->AzaliaConfigPtr = (UINT32)&mAzaliaConfig;
diff --git a/src/soc/intel/fsp_baytrail/lpe.c b/src/soc/intel/fsp_baytrail/lpe.c
index 8373b91..8baba3e 100644
--- a/src/soc/intel/fsp_baytrail/lpe.c
+++ b/src/soc/intel/fsp_baytrail/lpe.c
@@ -91,7 +91,7 @@
    struct soc_intel_fsp_baytrail_config *config;
    const char *freq_str;
-	config = dev->chip_info;
+	config = config_of(dev);
    switch (config->lpe_codec_clk_freq) {
    case 19:
    	freq_str = "19.2";
@@ -150,7 +150,7 @@
static void lpe_init(struct device *dev)
 {
-	struct soc_intel_fsp_baytrail_config *config = dev->chip_info;
+	struct soc_intel_fsp_baytrail_config *config = config_of(dev);
lpe_stash_firmware_info(dev);
diff --git a/src/soc/intel/fsp_baytrail/lpss.c b/src/soc/intel/fsp_baytrail/lpss.c
index d644138..154a70a 100644
--- a/src/soc/intel/fsp_baytrail/lpss.c
+++ b/src/soc/intel/fsp_baytrail/lpss.c
@@ -147,7 +147,7 @@
static void lpss_init(struct device *dev)
 {
-	struct soc_intel_fsp_baytrail_config *config = dev->chip_info;
+	struct soc_intel_fsp_baytrail_config *config = config_of(dev);
    int iosf_reg, nvs_index;
dev_ctl_reg(dev, &iosf_reg, &nvs_index);
diff --git a/src/soc/intel/fsp_broadwell_de/iou_complto.c b/src/soc/intel/fsp_broadwell_de/iou_complto.c
index dcc3071..c50cbb4 100644
--- a/src/soc/intel/fsp_broadwell_de/iou_complto.c
+++ b/src/soc/intel/fsp_broadwell_de/iou_complto.c
@@ -22,7 +22,7 @@
static void iou_init(struct device *dev)
 {
-	const config_t *config = dev->chip_info;
+	const config_t *config = config_of(dev);
    u16 devctl2;
/* pcie completion timeout
diff --git a/src/soc/intel/icelake/espi.c b/src/soc/intel/icelake/espi.c
index a98821c..efde625 100644
--- a/src/soc/intel/icelake/espi.c
+++ b/src/soc/intel/icelake/espi.c
@@ -48,7 +48,7 @@
void soc_get_gen_io_dec_range(const struct device *dev, uint32_t *gen_io_dec)
 {
-	const config_t *config = dev->chip_info;
+	const config_t *config = config_of(dev);
gen_io_dec[0] = config->gen1_dec;
    gen_io_dec[1] = config->gen2_dec;
diff --git a/src/soc/intel/icelake/memmap.c b/src/soc/intel/icelake/memmap.c
index 67f71da..317f0fb 100644
--- a/src/soc/intel/icelake/memmap.c
+++ b/src/soc/intel/icelake/memmap.c
@@ -166,7 +166,7 @@
    size_t reserve_mem_size;
    const struct soc_intel_icelake_config *config;
-	config = dev->chip_info;
+	config = config_of(dev);
/* Get PRMRR size */
    reserve_mem_base -= get_prmrr_size(reserve_mem_base, config);
diff --git a/src/soc/intel/icelake/pmutil.c b/src/soc/intel/icelake/pmutil.c
index 45f2a70..c738517 100644
--- a/src/soc/intel/icelake/pmutil.c
+++ b/src/soc/intel/icelake/pmutil.c
@@ -174,13 +174,7 @@
 {
    DEVTREE_CONST struct soc_intel_icelake_config *config;
-	/* Look up the device in devicetree */
-	DEVTREE_CONST struct device *dev = pcidev_path_on_root(PCH_DEVFN_PMC);
-	if (!dev || !dev->chip_info) {
-		printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n");
-		return;
-	}
-	config = dev->chip_info;
+	config = config_of_path(PCH_DEVFN_PMC);
/* Assign to out variable */
    *dw0 = config->gpe0_dw0;
diff --git a/src/soc/intel/icelake/romstage/fsp_params.c b/src/soc/intel/icelake/romstage/fsp_params.c
index 420c427..87f28b4 100644
--- a/src/soc/intel/icelake/romstage/fsp_params.c
+++ b/src/soc/intel/icelake/romstage/fsp_params.c
@@ -65,11 +65,11 @@
void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
 {
-	const struct device *dev = pcidev_on_root(0, 0);
-	assert(dev != NULL);
-	const struct soc_intel_icelake_config *config = dev->chip_info;
+	const struct soc_intel_icelake_config *config;
    FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;
+	config = config_of_path(SA_DEVFN_ROOT);
+
    soc_memory_init_params(m_cfg, config);
/* Enable SMBus controller based on config */
diff --git a/src/soc/intel/icelake/sd.c b/src/soc/intel/icelake/sd.c
index 4d84bb4..f7c0eb3 100644
--- a/src/soc/intel/icelake/sd.c
+++ b/src/soc/intel/icelake/sd.c
@@ -18,7 +18,7 @@
int sd_fill_soc_gpio_info(struct acpi_gpio *gpio, struct device *dev)
 {
-	config_t *config = dev->chip_info;
+	config_t *config = config_of(dev);
if (!config->sdcard_cd_gpio)
    	return -1;
diff --git a/src/soc/intel/icelake/smihandler.c b/src/soc/intel/icelake/smihandler.c
index 3d41ee0..8db2c3b 100644
--- a/src/soc/intel/icelake/smihandler.c
+++ b/src/soc/intel/icelake/smihandler.c
@@ -75,15 +75,8 @@
 void smihandler_soc_at_finalize(void)
 {
    const struct soc_intel_icelake_config *config;
-	const struct device *dev = pcidev_path_on_root(PCH_DEVFN_CSE);
-	if (!dev || !dev->chip_info) {
-		printk(BIOS_ERR, "%s: Could not find SoC devicetree config!\n",
-		       __func__);
-		return;
-	}
-
-	config = dev->chip_info;
+	config = config_of_path(PCH_DEVFN_CSE);
if (!config->HeciEnabled && CONFIG(HECI_DISABLE_USING_SMM))
    	pch_disable_heci();
diff --git a/src/soc/intel/quark/romstage/fsp2_0.c b/src/soc/intel/quark/romstage/fsp2_0.c
index a8bd26e..20f2ad7 100644
--- a/src/soc/intel/quark/romstage/fsp2_0.c
+++ b/src/soc/intel/quark/romstage/fsp2_0.c
@@ -104,7 +104,6 @@
 void platform_fsp_memory_init_params_cb(FSPM_UPD *fspm_upd, uint32_t version)
 {
    FSPM_ARCH_UPD *aupd;
-	const struct device *dev;
    const struct soc_intel_quark_config *config;
    void *rmu_data;
    size_t rmu_data_len;
@@ -120,10 +119,7 @@
    		"Microcode file (rmu.bin) not found.");
/* Locate the configuration data from devicetree.cb */
-	dev = pcidev_path_on_root(LPC_DEV_FUNC);
-	if (!dev)
-		die("ERROR - LPC device not found!");
-	config = dev->chip_info;
+	config = config_of_path(LPC_DEV_FUNC);
/* Update the architectural UPD values. */
    aupd = &fspm_upd->FspmArchUpd;
diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c
index 7fbe9e5..a7d5872 100644
--- a/src/soc/intel/skylake/chip.c
+++ b/src/soc/intel/skylake/chip.c
@@ -93,7 +93,7 @@
 void soc_silicon_init_params(SILICON_INIT_UPD *params)
 {
    struct device *dev = pcidev_path_on_root(PCH_DEVFN_LPC);
-	const struct soc_intel_skylake_config *config = dev->chip_info;
+	const struct soc_intel_skylake_config *config = config_of(dev);
    int i;
memcpy(params->SerialIoDevMode, config->SerialIoDevMode,
diff --git a/src/soc/intel/skylake/finalize.c b/src/soc/intel/skylake/finalize.c
index 34738f2..3c137c5 100644
--- a/src/soc/intel/skylake/finalize.c
+++ b/src/soc/intel/skylake/finalize.c
@@ -76,7 +76,7 @@
    intel_me_status();
pmcbase = pmc_mmio_regs();
-	config = dev->chip_info;
+	config = config_of(dev);
/*
     * Set low maximum temp value used for dynamic thermal sensor
@@ -117,7 +117,7 @@
    struct soc_intel_skylake_config *config;
    u8 reg8;
-	config = dev->chip_info;
+	config = config_of(dev);
/* Global SMI Lock */
    if (config->LockDownConfigGlobalSmi == 0) {
@@ -134,7 +134,7 @@
    dev = PCH_DEV_PMC;
/* Check if PMC is enabled, else return */
-	if (dev == NULL || dev->chip_info == NULL)
+	if (dev == NULL)
    	return;
printk(BIOS_DEBUG, "Finalizing chipset.\n");
diff --git a/src/soc/intel/skylake/graphics.c b/src/soc/intel/skylake/graphics.c
index 7efc65a..c06893e 100644
--- a/src/soc/intel/skylake/graphics.c
+++ b/src/soc/intel/skylake/graphics.c
@@ -36,7 +36,7 @@
static void graphics_setup_panel(struct device *dev)
 {
-	struct soc_intel_skylake_config *conf = dev->chip_info;
+	struct soc_intel_skylake_config *conf = config_of(dev);
    struct resource *mmio_res;
    uint8_t *base;
    u32 reg32;
diff --git a/src/soc/intel/skylake/irq.c b/src/soc/intel/skylake/irq.c
index 03cdb07..ddaffda 100644
--- a/src/soc/intel/skylake/irq.c
+++ b/src/soc/intel/skylake/irq.c
@@ -224,7 +224,7 @@
    uint32_t i, intdeventry;
    u8 irq_config[PCH_MAX_IRQ_CONFIG];
    const struct device *dev = pcidev_path_on_root(PCH_DEVFN_LPC);
-	const struct soc_intel_skylake_config *config = dev->chip_info;
+	const struct soc_intel_skylake_config *config = config_of(dev);
/* Get Device Int Count */
    intdeventry = ARRAY_SIZE(devintconfig);
@@ -295,7 +295,7 @@
void soc_pch_pirq_init(const struct device *dev)
 {
-	const config_t *config = dev->chip_info;
+	const config_t *config = config_of(dev);
    uint8_t pch_interrupt_routing[MAX_PXRC_CONFIG];
    struct device *irq_dev;
diff --git a/src/soc/intel/skylake/lpc.c b/src/soc/intel/skylake/lpc.c
index d8e5ccc..71ffb9a 100644
--- a/src/soc/intel/skylake/lpc.c
+++ b/src/soc/intel/skylake/lpc.c
@@ -69,7 +69,7 @@
void soc_get_gen_io_dec_range(const struct device *dev, uint32_t *gen_io_dec)
 {
-	const config_t *config = dev->chip_info;
+	const config_t *config = config_of(dev);
gen_io_dec[0] = config->gen1_dec;
    gen_io_dec[1] = config->gen2_dec;
@@ -98,7 +98,7 @@
void lpc_soc_init(struct device *dev)
 {
-	const config_t *const config = dev->chip_info;
+	const config_t *const config = config_of(dev);
/* Legacy initialization */
    isa_dma_init();
diff --git a/src/soc/intel/skylake/memmap.c b/src/soc/intel/skylake/memmap.c
index ff7edbc..1058300 100644
--- a/src/soc/intel/skylake/memmap.c
+++ b/src/soc/intel/skylake/memmap.c
@@ -207,7 +207,7 @@
    size_t reserve_mem_size;
    const struct soc_intel_skylake_config *config;
-	config = dev->chip_info;
+	config = config_of(dev);
/* Get PRMRR size */
    reserve_mem_base -= get_prmrr_size(reserve_mem_base, config);
diff --git a/src/soc/intel/skylake/pmutil.c b/src/soc/intel/skylake/pmutil.c
index 9732aa1..90f1b03 100644
--- a/src/soc/intel/skylake/pmutil.c
+++ b/src/soc/intel/skylake/pmutil.c
@@ -177,13 +177,7 @@
 {
    DEVTREE_CONST struct soc_intel_skylake_config *config;
-	/* Look up the device in devicetree */
-	DEVTREE_CONST struct device *dev = pcidev_path_on_root(PCH_DEVFN_PMC);
-	if (!dev || !dev->chip_info) {
-		printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n");
-		return;
-	}
-	config = dev->chip_info;
+	config = config_of_path(PCH_DEVFN_PMC);
/* Assign to out variable */
    *dw0 = config->gpe0_dw0;
diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c
index 2bbab47..2d0de2f 100644
--- a/src/soc/intel/skylake/romstage/romstage.c
+++ b/src/soc/intel/skylake/romstage/romstage.c
@@ -39,26 +39,26 @@
 /* SOC initialization before RAM is enabled */
 void soc_pre_ram_init(struct romstage_params *params)
 {
+	const struct soc_intel_skylake_config *config;
+
    /* Program MCHBAR and DMIBAR */
    systemagent_early_init();
-	const struct device *const dev = pcidev_path_on_root(PCH_DEVFN_LPC);
-	const struct soc_intel_skylake_config *const config =
-		dev ? dev->chip_info : NULL;
+	config = config_of_path(PCH_DEVFN_LPC);
+
    /* Force a full memory train if RMT is enabled */
-	params->disable_saved_data = config && config->Rmt;
+	params->disable_saved_data = config->Rmt;
 }
/* UPD parameters to be initialized before MemoryInit */
 void soc_memory_init_params(struct romstage_params *params,
    		    MEMORY_INIT_UPD *upd)
 {
-	const struct device *dev;
    const struct soc_intel_skylake_config *config;
/* Set the parameters for MemoryInit */
-	dev = pcidev_on_root(PCH_DEV_SLOT_LPC, 0);
-	config = dev->chip_info;
+
+	config = config_of_path(PCH_DEVFN_LPC);
/*
     * Set IGD stolen size to 64MB.  The FBC hardware for skylake does not
diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c
index 6884a32..2ab9800 100644
--- a/src/soc/intel/skylake/romstage/romstage_fsp20.c
+++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c
@@ -326,13 +326,11 @@
void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
 {
-	const struct device *dev;
    const struct soc_intel_skylake_config *config;
    FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;
    FSP_M_TEST_CONFIG *m_t_cfg = &mupd->FspmTestConfig;
-	dev = pcidev_on_root(PCH_DEV_SLOT_LPC, 0);
-	config = dev->chip_info;
+	config = config_of_path(LPC_DEV_FUNC);
soc_memory_init_params(m_cfg, config);
    soc_peg_init_params(m_cfg, m_t_cfg, config);
diff --git a/src/soc/intel/skylake/sd.c b/src/soc/intel/skylake/sd.c
index 571d3e7..a24d03f 100644
--- a/src/soc/intel/skylake/sd.c
+++ b/src/soc/intel/skylake/sd.c
@@ -18,7 +18,7 @@
int sd_fill_soc_gpio_info(struct acpi_gpio* gpio, struct device *dev)
 {
-	config_t *config = dev->chip_info;
+	config_t *config = config_of(dev);
/* Nothing to write if GPIO is not set in devicetree */
    if(!config->sdcard_cd_gpio_default && !config->sdcard_cd_gpio.pins[0])
diff --git a/src/soc/intel/skylake/systemagent.c b/src/soc/intel/skylake/systemagent.c
index bfaadfd..ea55262 100644
--- a/src/soc/intel/skylake/systemagent.c
+++ b/src/soc/intel/skylake/systemagent.c
@@ -52,12 +52,12 @@
    	{ GDXCBAR, GDXC_BASE_ADDRESS, GDXC_BASE_SIZE, "GDXCBAR" },
    	{ EDRAMBAR, EDRAM_BASE_ADDRESS, EDRAM_BASE_SIZE, "EDRAMBAR" },
    };
-	const struct soc_intel_skylake_config *const config = dev->chip_info;
+	const struct soc_intel_skylake_config *const config = config_of(dev);
sa_add_fixed_mmio_resources(dev, index, soc_fixed_resources,
    		ARRAY_SIZE(soc_fixed_resources));
-	if (!(config && config->ignore_vtd) && soc_is_vtd_capable()) {
+	if (!config->ignore_vtd && soc_is_vtd_capable()) {
    	if (igd_dev && igd_dev->enabled)
    		sa_add_fixed_mmio_resources(dev, index,
    				&soc_gfxvt_mmio_descriptor, 1);
diff --git a/src/soc/intel/skylake/thermal.c b/src/soc/intel/skylake/thermal.c
index 936543c..006f3ae 100644
--- a/src/soc/intel/skylake/thermal.c
+++ b/src/soc/intel/skylake/thermal.c
@@ -66,7 +66,7 @@
    uint16_t ltt_value;
    uint16_t trip_temp = DEFAULT_TRIP_TEMP;
-	config = dev->chip_info;
+	config = config_of(dev);
if (config->pch_trip_temp)
    	trip_temp = config->pch_trip_temp;
-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I0727a6b327410197cf32f598d1312737744386b3
Gerrit-Change-Number: 34328
Gerrit-PatchSet: 1
Gerrit-Owner: Kyösti Mälkki kyosti.malkki@gmail.com
Gerrit-Reviewer: David Guckian david.guckian@intel.com
Gerrit-Reviewer: Huang Jin huang.jin@intel.com
Gerrit-Reviewer: Kyösti Mälkki kyosti.malkki@gmail.com
Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org
Gerrit-Reviewer: Philipp Deppenwiese zaolin.daisuki@gmail.com
Gerrit-Reviewer: Vanny E vanessa.f.eusebio@intel.com
Gerrit-MessageType: newchange



    