Leroy P Leahy (leroy.p.leahy@intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13509
-gerrit
commit 46d4121e3b06826ef83ba6c4dee2032679d47f91 Author: Lee Leahy leroy.p.leahy@intel.com Date: Mon Feb 1 12:27:45 2016 -0800
mainboard/intel/galileo: Enable Serial Output
Add the code to enable debug serial output using HSUART1:
* Enable the code using Kconfig value ENABLE_BUILTIN_HSUART1 * Specify the portion of ESRAM to be used by romstage * Initialize the debug serial port
Testing: * Edit the src/mainboard/intel/galileo/Makefile.inc file * Add "select HAVE_FSP_PDAT_FILE" * Add "select HAVE_FSP_RAW_BIN" * Add "select HAVE_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Testing is successful if serial output is present on HSUART1 at 115200 baud, 8-bit, no parity
TEST=Build and run on Galileo
Change-Id: I91bf5257bd841ce9aa486887b35218336462ebea Signed-off-by: Lee Leahy leroy.p.leahy@intel.com --- src/mainboard/intel/galileo/Kconfig | 9 +++++++++ src/mainboard/intel/galileo/Makefile.inc | 2 ++ src/mainboard/intel/galileo/com_init.c | 27 +++++++++++++++++++++++++++ 3 files changed, 38 insertions(+)
diff --git a/src/mainboard/intel/galileo/Kconfig b/src/mainboard/intel/galileo/Kconfig index cae136f..1164765 100644 --- a/src/mainboard/intel/galileo/Kconfig +++ b/src/mainboard/intel/galileo/Kconfig @@ -18,9 +18,18 @@ if BOARD_INTEL_GALILEO config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_8192 + select ENABLE_BUILTIN_HSUART1 select PLATFORM_USES_FSP1_1 select SOC_INTEL_QUARK
+config DCACHE_RAM_BASE + hex + default 0x80070000 + +config DCACHE_RAM_SIZE + hex + default 0x00008000 + config MAINBOARD_DIR string default intel/galileo diff --git a/src/mainboard/intel/galileo/Makefile.inc b/src/mainboard/intel/galileo/Makefile.inc index 3ffba1c..4a79fe2 100644 --- a/src/mainboard/intel/galileo/Makefile.inc +++ b/src/mainboard/intel/galileo/Makefile.inc @@ -14,3 +14,5 @@ ##
CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp1_1/quark + +romstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += com_init.c diff --git a/src/mainboard/intel/galileo/com_init.c b/src/mainboard/intel/galileo/com_init.c new file mode 100644 index 0000000..28e1b0c --- /dev/null +++ b/src/mainboard/intel/galileo/com_init.c @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015-2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <fsp/car.h> +#include <device/pci.h> +#include <soc/iomap.h> +#include <soc/pci_devs.h> +#include <soc/romstage.h> + +void car_mainboard_pre_console_init(void) +{ + set_base_address_and_enable_uart(0, HSUART1_DEV, HSUART1_FUNC, + UART_BASE_ADDRESS); +}
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Leroy P Leahy