Change in coreboot[master]: soc/intel/common/block/acpi: Add LPM requirements support to PEPD _DSM
Attention is currently required from: Furquan Shaikh, Angel Pons, Michael Niewöhner, Patrick Rudolph, Karthik Ramasubramanian. Hello build bot (Jenkins), Cliff Huang, Furquan Shaikh, Angel Pons, Michael Niewöhner, Patrick Rudolph, Karthik Ramasubramanian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/56005
to look at the new patch set (#2).
Change subject: soc/intel/common/block/acpi: Add LPM requirements support to PEPD _DSM ......................................................................
soc/intel/common/block/acpi: Add LPM requirements support to PEPD _DSM
This patch adds support for the S0ix UUID in the Intel Power Engine _DSM method. This allows the ACPI tables to expose device/IP power states requirements for different system low power states
BUG=b:185437326 TEST=cat /sys/kernel/debug/pmc_core/substate_requirements Element | S0i2.0 | S0i3.0 | Status | USB2PLL_OFF_STS | Required | Required | Yes | PCIe/USB3.1_Gen2PLL_OFF_STS | Required | Required | | PCIe_Gen3PLL_OFF_STS | Required | Required | Yes | OPIOPLL_OFF_STS | Required | Required | | OCPLL_OFF_STS | Required | Required | Yes | MainPLL_OFF_STS | | Required | | MIPIPLL_OFF_STS | Required | Required | Yes | Fast_XTAL_Osc_OFF_STS | | Required | | AC_Ring_Osc_OFF_STS | Required | Required | Yes | SATAPLL_OFF_STS | Required | Required | Yes | XTAL_USB2PLL_OFF_STS | | Required | Yes | CSME_PG_STS | Required | Required | Yes | SATA_PG_STS | Required | Required | Yes | xHCI_PG_STS | Required | Required | | UFSX2_PG_STS | Required | Required | Yes | OTG_PG_STS | Required | Required | Yes | SPA_PG_STS | Required | Required | Yes | SPB_PG_STS | Required | Required | Yes | SPC_PG_STS | Required | Required | Yes | THC0_PG_STS | Required | Required | Yes | THC1_PG_STS | Required | Required | Yes | GBETSN_PG_STS | Required | Required | Yes | GBE_PG_STS | Required | Required | Yes | LPSS_PG_STS | Required | Required | | ADSP_D3_STS | | Required | Yes | xHCI0_D3_STS | Required | Required | | xDCI1_D3_STS | Required | Required | Yes | IS_D3_STS | Required | Required | | GBE_TSN_D3_STS | Required | Required | Yes | CPU_C10_REQ_STS_0 | Required | Required | Yes | CNVI_REQ_STS_6 | | Required | | ISH_REQ_STS_7 | | Required | Yes | MPHY_Core_DL_REQ_STS_16 | Required | Required | | Break-even_En_REQ_STS_17 | Required | Required | Yes | Auto-demo_En_REQ_STS_18 | Required | Required | Yes | Int_Timer_SS_Wake0_Pol_STS | Required | Required | | Int_Timer_SS_Wake1_Pol_STS | Required | Required | | Int_Timer_SS_Wake2_Pol_STS | Required | Required | | Int_Timer_SS_Wake3_Pol_STS | Required | Required | | Int_Timer_SS_Wake4_Pol_STS | Required | Required | | Int_Timer_SS_Wake5_Pol_STS | Required | Required | |
Signed-off-by: Tim Wawrzynczak twawrzynczak@chromium.org Change-Id: I542290bd5490aa6580a5ae2b266da3d78bc17e6b --- M src/soc/intel/common/block/acpi/Kconfig M src/soc/intel/common/block/acpi/pep.c M src/soc/intel/common/block/include/intelblocks/pmc_ipc.h 3 files changed, 73 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/56005/2
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Tim Wawrzynczak (Code Review)