Attention is currently required from: Felix Singer, Michał Żygowski, Michał Kopeć, Angel Pons. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62498 )
Change subject: mb/clevo/tgl-u: Add Clevo NV4x Tiger Lake laptop support ......................................................................
Patch Set 14:
(2 comments)
File src/mainboard/clevo/tgl-u/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/62498/comment/83360bc6_e966eee9 PS1, Line 58: register "LpmStateDisableMask" = " : LPM_S0i2_1 | : LPM_S0i2_2 | : LPM_S0i3_1 | : LPM_S0i3_2 | : LPM_S0i3_3 | : LPM_S0i3_4 :
Vendor firmware does this, I assumed there was a reason for it, but maybe there isn't? :D
-> see Michal's and my discussion in matrix ;) Intel docs don't state any specific requirements, so *probably* no need to disable s0i2.1. Who knows, maybe vendor fw has some problem caused by whatever... :S
File src/mainboard/clevo/tgl-u/variants/nv40mz/gpio.c:
https://review.coreboot.org/c/coreboot/+/62498/comment/8444c69a_7e9947d4 PS6, Line 129: //PAD_CFG_TERM_GPO(GPP_U4, 1, NONE, DEEP), /* DGPU_RST#_PCH */ : //PAD_CFG_TERM_GPO(GPP_U5, 1, NONE, DEEP), /* DGPU_PWR_EN */ :
Right, removed them from `gpio.c` altogether.
Oh, sorry, I should have been more clear. It should be configured in both. FSP would override the early settings when the GPIO isn't configured in ramstage.
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Michael Niewöhner (Code Review)