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Máté Kukri has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77050?usp=email )
Change subject: haswell NRI: Initialise MPLL ......................................................................
Patch Set 4:
(1 comment)
Patchset:
PS4: This applies to the whole series, not just this commit, but this commit seems to have the most discussion.
First of, this is absolutely amazing work, and in an ideal world it should have been merged years ago *but*
- I've been looking at what it would take to reverse engineer Intel raminit algorithms using publically available datasheets and I/O tracing for the last few years and what kind of code that would result in - I've *also done* some static analysis of "MemoryInit.efi" from a Haswell mainboard to debug why it is failing when running via SerialICE - Without speculating *how* this was written, I think it would be extremely hard to justify how this code *is not* a derivative work of Intel's MRC
If this was written with access to NDA documentation with Intel's blessing, then please ignore this as my brainfart, but *if not* I don't really see how this can be DCO signed-off as GPLv2-or-later. In the latter case, the best use of this for this code is a source-available, inspectable replacement for the MRC, but probably shouldn't be merged into coreboot in my opinion.
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Máté Kukri (Code Review)