Change in coreboot[master]: mb/google/zork: remove indirection for dxio lane configuration

[Aaron Durbin (Code Review)]

Aaron Durbin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44029 )

Change subject: mb/google/zork: remove indirection for dxio lane configuration
......................................................................

mb/google/zork: remove indirection for dxio lane configuration

There was a mix of open coding DXIO logical lane numbers and clkreq
pins. And there are separate macros depending on the baseboard
as well as processor type. Remove the indirection and supply the values
directly in the descriptors.

BUG=b:162423378

Change-Id: I779cb0a514e3b668265e6039d6e7e7bd0f3d49ed
Signed-off-by: Aaron Durbin 
---
M src/mainboard/google/zork/variants/baseboard/fsps_baseboard_dalboz.c
M src/mainboard/google/zork/variants/baseboard/fsps_baseboard_trembyle.c
M src/mainboard/google/zork/variants/baseboard/include/baseboard/gpio.h
3 files changed, 21 insertions(+), 42 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/44029/1

diff --git a/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_dalboz.c b/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_dalboz.c
index 8d55db6..c6e63ad 100644
--- a/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_dalboz.c
+++ b/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_dalboz.c
@@ -18,45 +18,45 @@
    	// NVME SSD
    	.port_present = true,
    	.engine_type = PCIE_ENGINE,
-		.start_logical_lane = NVME_START_LANE,
-		.end_logical_lane = NVME_END_LANE,
+		.start_logical_lane = 4,
+		.end_logical_lane = 5,
    	.device_number = 1,
    	.function_number = 7,
    	.link_aspm = ASPM_L1,
    	.link_aspm_L1_1 = true,
    	.link_aspm_L1_2 = true,
    	.turn_off_unused_lanes = true,
-		.clk_req = NVME_CLKREQ,
+		.clk_req = CLK_REQ2,
    	.clk_pm_support = true,
    },
    {
    	// WLAN
    	.port_present = true,
    	.engine_type = PCIE_ENGINE,
-		.start_logical_lane = WLAN_START_LANE,
-		.end_logical_lane = WLAN_END_LANE,
+		.start_logical_lane = 0,
+		.end_logical_lane = 0,
    	.device_number = 1,
    	.function_number = 2,
    	.link_aspm = ASPM_L1,
    	.link_aspm_L1_1 = true,
    	.link_aspm_L1_2 = true,
    	.turn_off_unused_lanes = true,
-		.clk_req = WLAN_CLKREQ,
+		.clk_req = CLK_REQ0,
    	.clk_pm_support = true,
    },
    {
    	// SD Reader
    	.port_present = true,
    	.engine_type = PCIE_ENGINE,
-		.start_logical_lane = SD_START_LANE,
-		.end_logical_lane = SD_END_LANE,
+		.start_logical_lane = 1,
+		.end_logical_lane = 1,
    	.device_number = 1,
    	.function_number = 3,
    	.link_aspm = ASPM_L1,
    	.link_aspm_L1_1 = true,
    	.link_aspm_L1_2 = true,
    	.turn_off_unused_lanes = true,
-		.clk_req = SD_CLKREQ,
+		.clk_req = CLK_REQ1,
    }
 };

diff --git a/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_trembyle.c b/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_trembyle.c
index 75c2211..26a5d33 100644
--- a/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_trembyle.c
+++ b/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_trembyle.c
@@ -31,7 +31,7 @@
    	.link_aspm_L1_1 = true,
    	.link_aspm_L1_2 = true,
    	.turn_off_unused_lanes = true,
-		.clk_req = NVME_CLKREQ,
+		.clk_req = CLK_REQ4,
    },
    {
    	// WLAN
@@ -45,7 +45,7 @@
    	.link_aspm_L1_1 = true,
    	.link_aspm_L1_2 = true,
    	.turn_off_unused_lanes = true,
-		.clk_req = WLAN_CLKREQ,
+		.clk_req = CLK_REQ0,
    	.clk_pm_support = true,
    },
    {
@@ -60,7 +60,7 @@
    	.link_aspm_L1_1 = true,
    	.link_aspm_L1_2 = true,
    	.turn_off_unused_lanes = true,
-		.clk_req = SD_CLKREQ,
+		.clk_req = CLK_REQ1,
    }
 };

@@ -69,45 +69,45 @@
    	// NVME SSD
    	.port_present = true,
    	.engine_type = PCIE_ENGINE,
-		.start_logical_lane = NVME_START_LANE,
-		.end_logical_lane = NVME_END_LANE,
+		.start_logical_lane = 0,
+		.end_logical_lane = 1,
    	.device_number = 1,
    	.function_number = 7,
    	.link_aspm = ASPM_L1,
    	.link_aspm_L1_1 = true,
    	.link_aspm_L1_2 = true,
    	.turn_off_unused_lanes = true,
-		.clk_req = NVME_CLKREQ,
+		.clk_req = CLK_REQ4,
    	.clk_pm_support = true,
    },
    {
    	// WLAN
    	.port_present = true,
    	.engine_type = PCIE_ENGINE,
-		.start_logical_lane = WLAN_START_LANE,
-		.end_logical_lane = WLAN_END_LANE,
+		.start_logical_lane = 4,
+		.end_logical_lane = 4,
    	.device_number = 1,
    	.function_number = 2,
    	.link_aspm = ASPM_L1,
    	.link_aspm_L1_1 = true,
    	.link_aspm_L1_2 = true,
    	.turn_off_unused_lanes = true,
-		.clk_req = WLAN_CLKREQ,
+		.clk_req = CLK_REQ0,
    	.clk_pm_support = true,
    },
    {
    	// SD Reader
    	.port_present = true,
    	.engine_type = PCIE_ENGINE,
-		.start_logical_lane = SD_START_LANE,
-		.end_logical_lane = SD_END_LANE,
+		.start_logical_lane = 5,
+		.end_logical_lane = 5,
    	.device_number = 1,
    	.function_number = 3,
    	.link_aspm = ASPM_L1,
    	.link_aspm_L1_1 = true,
    	.link_aspm_L1_2 = true,
    	.turn_off_unused_lanes = true,
-		.clk_req = SD_CLKREQ,
+		.clk_req = CLK_REQ1,
    }
 };

diff --git a/src/mainboard/google/zork/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/zork/variants/baseboard/include/baseboard/gpio.h
index 84433e0..389f0e8 100644
--- a/src/mainboard/google/zork/variants/baseboard/include/baseboard/gpio.h
+++ b/src/mainboard/google/zork/variants/baseboard/include/baseboard/gpio.h
@@ -7,31 +7,10 @@
 #include <soc/gpio.h>
 #include <platform_descriptors.h>

-#define WLAN_CLKREQ		CLK_REQ0
-#define SD_CLKREQ		CLK_REQ1
-
-#if CONFIG(BOARD_GOOGLE_BASEBOARD_DALBOZ)
-#define NVME_START_LANE 4
-#define NVME_END_LANE 5
-#define WLAN_START_LANE 0
-#define WLAN_END_LANE 0
-#define SD_START_LANE 1
-#define SD_END_LANE 1
-#else
-#define NVME_START_LANE 0
-#define NVME_END_LANE 1
-#define WLAN_START_LANE 4
-#define WLAN_END_LANE 4
-#define SD_START_LANE 5
-#define SD_END_LANE 5
-#endif
-
 #if CONFIG(BOARD_GOOGLE_BASEBOARD_TREMBYLE)
 #define EC_IN_RW_OD		GPIO_130
-#define NVME_CLKREQ		CLK_REQ4
 #else
 #define EC_IN_RW_OD		GPIO_11
-#define NVME_CLKREQ		CLK_REQ2
 #endif

/* SPI Write protect */

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44029 )

Change subject: mb/google/zork: remove indirection for dxio lane configuration
......................................................................

Patch Set 1: Code-Review+2

[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44029 )

Change subject: mb/google/zork: remove indirection for dxio lane configuration
......................................................................

Patch Set 1: Code-Review+2

[Felix Held (Code Review)]

Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44029 )

Change subject: mb/google/zork: remove indirection for dxio lane configuration
......................................................................

Patch Set 1: Code-Review+2

removing the one layer of indirection makes things easier to read and verify

[Aaron Durbin (Code Review)]

Aaron Durbin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/44029 )

Change subject: mb/google/zork: remove indirection for dxio lane configuration
......................................................................

mb/google/zork: remove indirection for dxio lane configuration

There was a mix of open coding DXIO logical lane numbers and clkreq
pins. And there are separate macros depending on the baseboard
as well as processor type. Remove the indirection and supply the values
directly in the descriptors.

BUG=b:162423378

Change-Id: I779cb0a514e3b668265e6039d6e7e7bd0f3d49ed
Signed-off-by: Aaron Durbin 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44029
Tested-by: build bot (Jenkins) 
Reviewed-by: Furquan Shaikh 
Reviewed-by: Angel Pons 
Reviewed-by: Felix Held 
---
M src/mainboard/google/zork/variants/baseboard/fsps_baseboard_dalboz.c
M src/mainboard/google/zork/variants/baseboard/fsps_baseboard_trembyle.c
M src/mainboard/google/zork/variants/baseboard/include/baseboard/gpio.h
3 files changed, 21 insertions(+), 42 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Felix Held: Looks good to me, approved
  Furquan Shaikh: Looks good to me, approved
  Angel Pons: Looks good to me, approved

diff --git a/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_dalboz.c b/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_dalboz.c
index 8d55db6..c6e63ad 100644
--- a/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_dalboz.c
+++ b/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_dalboz.c
@@ -18,45 +18,45 @@
    	// NVME SSD
    	.port_present = true,
    	.engine_type = PCIE_ENGINE,
-		.start_logical_lane = NVME_START_LANE,
-		.end_logical_lane = NVME_END_LANE,
+		.start_logical_lane = 4,
+		.end_logical_lane = 5,
    	.device_number = 1,
    	.function_number = 7,
    	.link_aspm = ASPM_L1,
    	.link_aspm_L1_1 = true,
    	.link_aspm_L1_2 = true,
    	.turn_off_unused_lanes = true,
-		.clk_req = NVME_CLKREQ,
+		.clk_req = CLK_REQ2,
    	.clk_pm_support = true,
    },
    {
    	// WLAN
    	.port_present = true,
    	.engine_type = PCIE_ENGINE,
-		.start_logical_lane = WLAN_START_LANE,
-		.end_logical_lane = WLAN_END_LANE,
+		.start_logical_lane = 0,
+		.end_logical_lane = 0,
    	.device_number = 1,
    	.function_number = 2,
    	.link_aspm = ASPM_L1,
    	.link_aspm_L1_1 = true,
    	.link_aspm_L1_2 = true,
    	.turn_off_unused_lanes = true,
-		.clk_req = WLAN_CLKREQ,
+		.clk_req = CLK_REQ0,
    	.clk_pm_support = true,
    },
    {
    	// SD Reader
    	.port_present = true,
    	.engine_type = PCIE_ENGINE,
-		.start_logical_lane = SD_START_LANE,
-		.end_logical_lane = SD_END_LANE,
+		.start_logical_lane = 1,
+		.end_logical_lane = 1,
    	.device_number = 1,
    	.function_number = 3,
    	.link_aspm = ASPM_L1,
    	.link_aspm_L1_1 = true,
    	.link_aspm_L1_2 = true,
    	.turn_off_unused_lanes = true,
-		.clk_req = SD_CLKREQ,
+		.clk_req = CLK_REQ1,
    }
 };

diff --git a/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_trembyle.c b/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_trembyle.c
index 75c2211..26a5d33 100644
--- a/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_trembyle.c
+++ b/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_trembyle.c
@@ -31,7 +31,7 @@
    	.link_aspm_L1_1 = true,
    	.link_aspm_L1_2 = true,
    	.turn_off_unused_lanes = true,
-		.clk_req = NVME_CLKREQ,
+		.clk_req = CLK_REQ4,
    },
    {
    	// WLAN
@@ -45,7 +45,7 @@
    	.link_aspm_L1_1 = true,
    	.link_aspm_L1_2 = true,
    	.turn_off_unused_lanes = true,
-		.clk_req = WLAN_CLKREQ,
+		.clk_req = CLK_REQ0,
    	.clk_pm_support = true,
    },
    {
@@ -60,7 +60,7 @@
    	.link_aspm_L1_1 = true,
    	.link_aspm_L1_2 = true,
    	.turn_off_unused_lanes = true,
-		.clk_req = SD_CLKREQ,
+		.clk_req = CLK_REQ1,
    }
 };

@@ -69,45 +69,45 @@
    	// NVME SSD
    	.port_present = true,
    	.engine_type = PCIE_ENGINE,
-		.start_logical_lane = NVME_START_LANE,
-		.end_logical_lane = NVME_END_LANE,
+		.start_logical_lane = 0,
+		.end_logical_lane = 1,
    	.device_number = 1,
    	.function_number = 7,
    	.link_aspm = ASPM_L1,
    	.link_aspm_L1_1 = true,
    	.link_aspm_L1_2 = true,
    	.turn_off_unused_lanes = true,
-		.clk_req = NVME_CLKREQ,
+		.clk_req = CLK_REQ4,
    	.clk_pm_support = true,
    },
    {
    	// WLAN
    	.port_present = true,
    	.engine_type = PCIE_ENGINE,
-		.start_logical_lane = WLAN_START_LANE,
-		.end_logical_lane = WLAN_END_LANE,
+		.start_logical_lane = 4,
+		.end_logical_lane = 4,
    	.device_number = 1,
    	.function_number = 2,
    	.link_aspm = ASPM_L1,
    	.link_aspm_L1_1 = true,
    	.link_aspm_L1_2 = true,
    	.turn_off_unused_lanes = true,
-		.clk_req = WLAN_CLKREQ,
+		.clk_req = CLK_REQ0,
    	.clk_pm_support = true,
    },
    {
    	// SD Reader
    	.port_present = true,
    	.engine_type = PCIE_ENGINE,
-		.start_logical_lane = SD_START_LANE,
-		.end_logical_lane = SD_END_LANE,
+		.start_logical_lane = 5,
+		.end_logical_lane = 5,
    	.device_number = 1,
    	.function_number = 3,
    	.link_aspm = ASPM_L1,
    	.link_aspm_L1_1 = true,
    	.link_aspm_L1_2 = true,
    	.turn_off_unused_lanes = true,
-		.clk_req = SD_CLKREQ,
+		.clk_req = CLK_REQ1,
    }
 };

diff --git a/src/mainboard/google/zork/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/zork/variants/baseboard/include/baseboard/gpio.h
index 84433e0..389f0e8 100644
--- a/src/mainboard/google/zork/variants/baseboard/include/baseboard/gpio.h
+++ b/src/mainboard/google/zork/variants/baseboard/include/baseboard/gpio.h
@@ -7,31 +7,10 @@
 #include <soc/gpio.h>
 #include <platform_descriptors.h>

-#define WLAN_CLKREQ		CLK_REQ0
-#define SD_CLKREQ		CLK_REQ1
-
-#if CONFIG(BOARD_GOOGLE_BASEBOARD_DALBOZ)
-#define NVME_START_LANE 4
-#define NVME_END_LANE 5
-#define WLAN_START_LANE 0
-#define WLAN_END_LANE 0
-#define SD_START_LANE 1
-#define SD_END_LANE 1
-#else
-#define NVME_START_LANE 0
-#define NVME_END_LANE 1
-#define WLAN_START_LANE 4
-#define WLAN_END_LANE 4
-#define SD_START_LANE 5
-#define SD_END_LANE 5
-#endif
-
 #if CONFIG(BOARD_GOOGLE_BASEBOARD_TREMBYLE)
 #define EC_IN_RW_OD		GPIO_130
-#define NVME_CLKREQ		CLK_REQ4
 #else
 #define EC_IN_RW_OD		GPIO_11
-#define NVME_CLKREQ		CLK_REQ2
 #endif

/* SPI Write protect */