Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41835 )
Change subject: soc/amd/picasso/acpi: Remove hardcoded FCH IRQ numbers ......................................................................
soc/amd/picasso/acpi: Remove hardcoded FCH IRQ numbers
Modify the FCH ACPI devices to query the PCI IRQ mapping registers for their current IRQ numbers.
BUG=b:139429446, b:154756391 TEST=Boot trembyle and see that I2C and UART devices are finally functional.
Signed-off-by: Raul E Rangel rrangel@chromium.org Change-Id: I8f2035f74240ead4089ff4d503dfbeb447cf8de4 --- M src/soc/amd/picasso/acpi/pcie.asl M src/soc/amd/picasso/acpi/sb_fch.asl 2 files changed, 239 insertions(+), 49 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/41835/1
diff --git a/src/soc/amd/picasso/acpi/pcie.asl b/src/soc/amd/picasso/acpi/pcie.asl index 2bbfec56..561a3f8 100644 --- a/src/soc/amd/picasso/acpi/pcie.asl +++ b/src/soc/amd/picasso/acpi/pcie.asl @@ -16,6 +16,21 @@ PIRG, 0x00000008, /* Index 6: INTG */ PIRH, 0x00000008, /* Index 7: INTH */
+ Offset (0x62), + PGPI, 0x00000008, /* Index 0x62: GPIO */ + + Offset (0x70), + PI20, 0x00000008, /* Index 0x70: I2C0 */ + PI21, 0x00000008, /* Index 0x71: I2C1 */ + PI22, 0x00000008, /* Index 0x72: I2C2 */ + PI23, 0x00000008, /* Index 0x73: I2C3 */ + PUA0, 0x00000008, /* Index 0x74: UART0 */ + PUA1, 0x00000008, /* Index 0x75: UART1 */ + PI24, 0x00000008, /* Index 0x76: I2C4 */ + PI25, 0x00000008, /* Index 0x77: I2C5 */ + PUA2, 0x00000008, /* Index 0x78: UART2 */ + PUA3, 0x00000008, /* Index 0x79: UART3 */ + /* IO-APIC IRQs */ Offset (0x80), IORA, 0x00000008, /* Index 0x80: INTA */ @@ -26,6 +41,21 @@ IORF, 0x00000008, /* Index 0x85: INTF */ IORG, 0x00000008, /* Index 0x86: INTG */ IORH, 0x00000008, /* Index 0x87: INTH */ + + Offset (0xE2), + IGPI, 0x00000008, /* Index 0xE2: GPIO */ + + Offset (0xF0), + II20, 0x00000008, /* Index 0xF0: I2C0 */ + II21, 0x00000008, /* Index 0xF1: I2C1 */ + II22, 0x00000008, /* Index 0xF2: I2C2 */ + II23, 0x00000008, /* Index 0xF3: I2C3 */ + IUA0, 0x00000008, /* Index 0xF4: UART0 */ + IUA1, 0x00000008, /* Index 0xF5: UART1 */ + II24, 0x00000008, /* Index 0xF6: I2C4 */ + II25, 0x00000008, /* Index 0xF7: I2C5 */ + IUA2, 0x00000008, /* Index 0xF8: UART2 */ + IUA3, 0x00000008, /* Index 0xF9: UART3 */ }
/* PCI Error control register */ diff --git a/src/soc/amd/picasso/acpi/sb_fch.asl b/src/soc/amd/picasso/acpi/sb_fch.asl index f8df3c0..197da3a 100644 --- a/src/soc/amd/picasso/acpi/sb_fch.asl +++ b/src/soc/amd/picasso/acpi/sb_fch.asl @@ -26,12 +26,30 @@ Name (_UID, 0) Name (_DDN, GPIO_DEVICE_DESC)
- Name (_CRS, ResourceTemplate() - { - Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) - { 7 } - Memory32Fixed (ReadWrite, 0xFED81500, 0x300) - }) + Method(_CRS, 0) { + local0=ResourceTemplate(){ + Interrupt ( + ResourceConsumer, + Level, + ActiveLow, + Exclusive, , , IRQR) + { 0 } + Memory32Fixed (ReadWrite, 0xFED81500, 0x300) + } + CreateDWordField(local0, IRQR._INT, IRQN) + If (PMOD) { + IRQN=IGPI + } Else { + IRQN=PGPI + } + If (IRQN == 0x1f) { + Return(ResourceTemplate(){ + Memory32Fixed (ReadWrite, 0xFED81500, 0x300) + }) + } Else { + Return(local0) + } + }
Method (_STA, 0x0, NotSerialized) { @@ -43,12 +61,33 @@ { Name (_HID, "AMD0020") Name (_UID, 0x0) - Name (_CRS, ResourceTemplate() - { - IRQ (Edge, ActiveHigh, Exclusive) { 10 } - Memory32Fixed (ReadWrite, APU_UART0_BASE, 0x1000) - Memory32Fixed (ReadWrite, APU_DMAC0_BASE, 0x1000) - }) + Method(_CRS, 0) { + local0=ResourceTemplate(){ + Interrupt ( + ResourceConsumer, + Edge, + ActiveHigh, + Exclusive, , , IRQR) + { 0 } + Memory32Fixed (ReadWrite, APU_UART0_BASE, 0x1000) + Memory32Fixed (ReadWrite, APU_DMAC0_BASE, 0x1000) + } + CreateDWordField(local0, IRQR._INT, IRQN) + If (PMOD) { + IRQN=IUA0 + } Else { + IRQN=PUA0 + } + If (IRQN == 0x1f) { + Return(ResourceTemplate(){ + Memory32Fixed (ReadWrite, APU_UART0_BASE, 0x1000) + Memory32Fixed (ReadWrite, APU_DMAC0_BASE, 0x1000) + }) + } Else { + Return(local0) + } + } + Method (_STA, 0x0, NotSerialized) { Return (0x0F) @@ -58,28 +97,69 @@ Device (FUR1) { Name (_HID, "AMD0020") Name (_UID, 0x1) - Name (_CRS, ResourceTemplate() - { - IRQ (Edge, ActiveHigh, Exclusive) { 11 } - Memory32Fixed (ReadWrite, APU_UART1_BASE, 0x1000) - Memory32Fixed (ReadWrite, APU_DMAC1_BASE, 0x1000) - }) + Method(_CRS, 0) { + local0=ResourceTemplate(){ + Interrupt ( + ResourceConsumer, + Edge, + ActiveHigh, + Exclusive, , , IRQR) + { 0 } + Memory32Fixed (ReadWrite, APU_UART1_BASE, 0x1000) + Memory32Fixed (ReadWrite, APU_DMAC1_BASE, 0x1000) + } + CreateDWordField(local0, IRQR._INT, IRQN) + If (PMOD) { + IRQN=IUA1 + } Else { + IRQN=PUA1 + } + If (IRQN == 0x1f) { + Return(ResourceTemplate(){ + Memory32Fixed (ReadWrite, APU_UART1_BASE, 0x1000) + Memory32Fixed (ReadWrite, APU_DMAC1_BASE, 0x1000) + }) + } Else { + Return(local0) + } + } + Method (_STA, 0x0, NotSerialized) { Return (0x0F) } }
-Device (FUR2) -{ +Device (FUR2) { Name (_HID, "AMD0020") - Name (_UID, 0x0) - Name (_CRS, ResourceTemplate() - { - IRQ (Edge, ActiveHigh, Exclusive) { 15 } - Memory32Fixed (ReadWrite, APU_UART2_BASE, 0x1000) - Memory32Fixed (ReadWrite, APU_DMAC2_BASE, 0x1000) - }) + Name (_UID, 0x2) + Method(_CRS, 0) { + local0=ResourceTemplate(){ + Interrupt ( + ResourceConsumer, + Edge, + ActiveHigh, + Exclusive, , , IRQR) + { 0 } + Memory32Fixed (ReadWrite, APU_UART2_BASE, 0x1000) + Memory32Fixed (ReadWrite, APU_DMAC2_BASE, 0x1000) + } + CreateDWordField(local0, IRQR._INT, IRQN) + If (PMOD) { + IRQN=IUA2 + } Else { + IRQN=PUA2 + } + If (IRQN == 0x1f) { + Return(ResourceTemplate(){ + Memory32Fixed (ReadWrite, APU_UART1_BASE, 0x1000) + Memory32Fixed (ReadWrite, APU_DMAC1_BASE, 0x1000) + }) + } Else { + Return(local0) + } + } + Method (_STA, 0x0, NotSerialized) { Return (0x0F) @@ -88,13 +168,34 @@
Device (FUR3) { Name (_HID, "AMD0020") - Name (_UID, 0x1) - Name (_CRS, ResourceTemplate() - { - IRQ (Edge, ActiveHigh, Exclusive) { 5 } - Memory32Fixed (ReadWrite, APU_UART3_BASE, 0x1000) - Memory32Fixed (ReadWrite, APU_DMAC3_BASE, 0x1000) - }) + Name (_UID, 0x3) + Method(_CRS, 0) { + local0=ResourceTemplate(){ + Interrupt ( + ResourceConsumer, + Edge, + ActiveHigh, + Exclusive, , , IRQR) + { 0 } + Memory32Fixed (ReadWrite, APU_UART1_BASE, 0x1000) + Memory32Fixed (ReadWrite, APU_DMAC1_BASE, 0x1000) + } + CreateDWordField(local0, IRQR._INT, IRQN) + If (PMOD) { + IRQN=IUA3 + } Else { + IRQN=PUA3 + } + If (IRQN == 0x1f) { + Return(ResourceTemplate(){ + Memory32Fixed (ReadWrite, APU_UART3_BASE, 0x1000) + Memory32Fixed (ReadWrite, APU_DMAC3_BASE, 0x1000) + }) + } Else { + Return(local0) + } + } + Method (_STA, 0x0, NotSerialized) { Return (0x0F) @@ -104,11 +205,30 @@ Device (I2C2) { Name (_HID, "AMD0010") Name (_UID, 0x2) - Name (_CRS, ResourceTemplate() - { - IRQ (Edge, ActiveHigh, Exclusive) { 4 } - Memory32Fixed (ReadWrite, APU_I2C2_BASE, 0x1000) - }) + Method(_CRS, 0) { + local0=ResourceTemplate(){ + Interrupt ( + ResourceConsumer, + Edge, + ActiveHigh, + Exclusive, , , IRQR) + { 0 } + Memory32Fixed (ReadWrite, APU_I2C2_BASE, 0x1000) + } + CreateDWordField(local0, IRQR._INT, IRQN) + If (PMOD) { + IRQN=II22 + } Else { + IRQN=PI22 + } + If (IRQN == 0x1f) { + Return(ResourceTemplate(){ + Memory32Fixed (ReadWrite, APU_I2C2_BASE, 0x1000) + }) + } Else { + Return(local0) + } + }
Method (_STA, 0x0, NotSerialized) { @@ -120,24 +240,64 @@ { Name (_HID, "AMD0010") Name (_UID, 0x3) - Name (_CRS, ResourceTemplate() { - IRQ (Edge, ActiveHigh, Exclusive) { 6 } - Memory32Fixed(ReadWrite, APU_I2C3_BASE, 0x1000) - }) + Method(_CRS, 0) { + local0=ResourceTemplate(){ + Interrupt ( + ResourceConsumer, + Edge, + ActiveHigh, + Exclusive, , , IRQR) + { 0 } + Memory32Fixed (ReadWrite, APU_I2C3_BASE, 0x1000) + } + CreateDWordField(local0, IRQR._INT, IRQN) + If (PMOD) { + IRQN=II23 + } Else { + IRQN=PI23 + } + If (IRQN == 0x1f) { + Return(ResourceTemplate(){ + Memory32Fixed (ReadWrite, APU_I2C3_BASE, 0x1000) + }) + } Else { + Return(local0) + } + } Method (_STA, 0x0, NotSerialized) { Return (0x0F) } }
-Device (I2C4) -{ +Device (I2C4) { Name (_HID, "AMD0010") Name (_UID, 0x4) - Name (_CRS, ResourceTemplate() { - IRQ (Edge, ActiveHigh, Exclusive) { 14 } - Memory32Fixed(ReadWrite, APU_I2C4_BASE, 0x1000) - }) + Method(_CRS, 0) { + local0=ResourceTemplate(){ + Interrupt ( + ResourceConsumer, + Edge, + ActiveHigh, + Exclusive, , , IRQR) + { 0 } + Memory32Fixed (ReadWrite, APU_I2C4_BASE, 0x1000) + } + CreateDWordField(local0, IRQR._INT, IRQN) + If (PMOD) { + IRQN=II24 + } Else { + IRQN=PI24 + } + If (IRQN == 0x1f) { + Return(ResourceTemplate(){ + Memory32Fixed (ReadWrite, APU_I2C4_BASE, 0x1000) + }) + } Else { + Return(local0) + } + } + Method (_STA, 0x0, NotSerialized) { Return (0x0F)
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41835 )
Change subject: soc/amd/picasso/acpi: Remove hardcoded FCH IRQ numbers ......................................................................
Patch Set 1:
(11 comments)
https://review.coreboot.org/c/coreboot/+/41835/1/src/soc/amd/picasso/acpi/sb... File src/soc/amd/picasso/acpi/sb_fch.asl:
https://review.coreboot.org/c/coreboot/+/41835/1/src/soc/amd/picasso/acpi/sb... PS1, Line 29: ( nit: space before (
https://review.coreboot.org/c/coreboot/+/41835/1/src/soc/amd/picasso/acpi/sb... PS1, Line 30: ResourceTemplate Name (RBUF, ResourceTemplate() { ... }
https://review.coreboot.org/c/coreboot/+/41835/1/src/soc/amd/picasso/acpi/sb... PS1, Line 30: { space before {
https://review.coreboot.org/c/coreboot/+/41835/1/src/soc/amd/picasso/acpi/sb... PS1, Line 30: local0 Local0?
https://review.coreboot.org/c/coreboot/+/41835/1/src/soc/amd/picasso/acpi/sb... PS1, Line 39: ( space before (
https://review.coreboot.org/c/coreboot/+/41835/1/src/soc/amd/picasso/acpi/sb... PS1, Line 41: = spaces around =
https://review.coreboot.org/c/coreboot/+/41835/1/src/soc/amd/picasso/acpi/sb... PS1, Line 43: = spaces around =
https://review.coreboot.org/c/coreboot/+/41835/1/src/soc/amd/picasso/acpi/sb... PS1, Line 46: { space before {
https://review.coreboot.org/c/coreboot/+/41835/1/src/soc/amd/picasso/acpi/sb... PS1, Line 46: ( space before (
https://review.coreboot.org/c/coreboot/+/41835/1/src/soc/amd/picasso/acpi/sb... PS1, Line 50: local0 If you change to RBUF, then this will have to be updated to RBUF.
https://review.coreboot.org/c/coreboot/+/41835/1/src/soc/amd/picasso/acpi/sb... PS1, Line 50: ( space before (
Hello build bot (Jenkins), Furquan Shaikh, Aaron Durbin, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/41835
to look at the new patch set (#2).
Change subject: soc/amd/picasso/acpi: Remove hardcoded FCH IRQ numbers ......................................................................
soc/amd/picasso/acpi: Remove hardcoded FCH IRQ numbers
Modify the FCH ACPI devices to query the PCI IRQ mapping registers for their current IRQ numbers.
BUG=b:139429446, b:154756391 TEST=Boot trembyle and see that I2C and UART devices are finally functional.
Signed-off-by: Raul E Rangel rrangel@chromium.org Change-Id: I8f2035f74240ead4089ff4d503dfbeb447cf8de4 --- M src/soc/amd/picasso/acpi/pcie.asl M src/soc/amd/picasso/acpi/sb_fch.asl 2 files changed, 240 insertions(+), 50 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/41835/2
Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41835 )
Change subject: soc/amd/picasso/acpi: Remove hardcoded FCH IRQ numbers ......................................................................
Uploaded patch set 2.
(11 comments)
https://review.coreboot.org/c/coreboot/+/41835/1/src/soc/amd/picasso/acpi/sb... File src/soc/amd/picasso/acpi/sb_fch.asl:
https://review.coreboot.org/c/coreboot/+/41835/1/src/soc/amd/picasso/acpi/sb... PS1, Line 29: (
nit: space before (
Done
https://review.coreboot.org/c/coreboot/+/41835/1/src/soc/amd/picasso/acpi/sb... PS1, Line 30: {
space before {
Done
https://review.coreboot.org/c/coreboot/+/41835/1/src/soc/amd/picasso/acpi/sb... PS1, Line 30: ResourceTemplate
Name (RBUF, ResourceTemplate() { […]
Done
https://review.coreboot.org/c/coreboot/+/41835/1/src/soc/amd/picasso/acpi/sb... PS1, Line 30: local0
Local0?
Done
https://review.coreboot.org/c/coreboot/+/41835/1/src/soc/amd/picasso/acpi/sb... PS1, Line 39: (
space before (
Done
https://review.coreboot.org/c/coreboot/+/41835/1/src/soc/amd/picasso/acpi/sb... PS1, Line 41: =
spaces around =
Done
https://review.coreboot.org/c/coreboot/+/41835/1/src/soc/amd/picasso/acpi/sb... PS1, Line 43: =
spaces around =
Done
https://review.coreboot.org/c/coreboot/+/41835/1/src/soc/amd/picasso/acpi/sb... PS1, Line 46: (
space before (
Done
https://review.coreboot.org/c/coreboot/+/41835/1/src/soc/amd/picasso/acpi/sb... PS1, Line 46: {
space before {
Done
https://review.coreboot.org/c/coreboot/+/41835/1/src/soc/amd/picasso/acpi/sb... PS1, Line 50: (
space before (
Done
https://review.coreboot.org/c/coreboot/+/41835/1/src/soc/amd/picasso/acpi/sb... PS1, Line 50: local0
If you change to RBUF, then this will have to be updated to RBUF.
Done
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41835 )
Change subject: soc/amd/picasso/acpi: Remove hardcoded FCH IRQ numbers ......................................................................
Patch Set 2:
(4 comments)
https://review.coreboot.org/c/coreboot/+/41835/2/src/soc/amd/picasso/acpi/sb... File src/soc/amd/picasso/acpi/sb_fch.asl:
https://review.coreboot.org/c/coreboot/+/41835/2/src/soc/amd/picasso/acpi/sb... PS2, Line 155: UART1 UART2
https://review.coreboot.org/c/coreboot/+/41835/2/src/soc/amd/picasso/acpi/sb... PS2, Line 156: DMAC1 DMAC2
https://review.coreboot.org/c/coreboot/+/41835/2/src/soc/amd/picasso/acpi/sb... PS2, Line 180: UART1 UART3
https://review.coreboot.org/c/coreboot/+/41835/2/src/soc/amd/picasso/acpi/sb... PS2, Line 181: DMAC1 DMAC3
Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41835 )
Change subject: soc/amd/picasso/acpi: Remove hardcoded FCH IRQ numbers ......................................................................
Uploaded patch set 3.
Hello build bot (Jenkins), Furquan Shaikh, Aaron Durbin, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/41835
to look at the new patch set (#3).
Change subject: soc/amd/picasso/acpi: Remove hardcoded FCH IRQ numbers ......................................................................
soc/amd/picasso/acpi: Remove hardcoded FCH IRQ numbers
Modify the FCH ACPI devices to query the PCI IRQ mapping registers for their current IRQ numbers.
BUG=b:139429446, b:154756391 TEST=Boot trembyle and see that I2C and UART devices are finally functional.
Signed-off-by: Raul E Rangel rrangel@chromium.org Change-Id: I8f2035f74240ead4089ff4d503dfbeb447cf8de4 --- M src/soc/amd/picasso/acpi/pcie.asl M src/soc/amd/picasso/acpi/sb_fch.asl 2 files changed, 240 insertions(+), 50 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/41835/3
Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41835 )
Change subject: soc/amd/picasso/acpi: Remove hardcoded FCH IRQ numbers ......................................................................
Patch Set 3:
(4 comments)
https://review.coreboot.org/c/coreboot/+/41835/2/src/soc/amd/picasso/acpi/sb... File src/soc/amd/picasso/acpi/sb_fch.asl:
https://review.coreboot.org/c/coreboot/+/41835/2/src/soc/amd/picasso/acpi/sb... PS2, Line 155: UART1
UART2
Oops!
https://review.coreboot.org/c/coreboot/+/41835/2/src/soc/amd/picasso/acpi/sb... PS2, Line 156: DMAC1
DMAC2
Done
https://review.coreboot.org/c/coreboot/+/41835/2/src/soc/amd/picasso/acpi/sb... PS2, Line 180: UART1
UART3
Done
https://review.coreboot.org/c/coreboot/+/41835/2/src/soc/amd/picasso/acpi/sb... PS2, Line 181: DMAC1
DMAC3
Done
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41835 )
Change subject: soc/amd/picasso/acpi: Remove hardcoded FCH IRQ numbers ......................................................................
Patch Set 3: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/41835 )
Change subject: soc/amd/picasso/acpi: Remove hardcoded FCH IRQ numbers ......................................................................
soc/amd/picasso/acpi: Remove hardcoded FCH IRQ numbers
Modify the FCH ACPI devices to query the PCI IRQ mapping registers for their current IRQ numbers.
BUG=b:139429446, b:154756391 TEST=Boot trembyle and see that I2C and UART devices are finally functional.
Signed-off-by: Raul E Rangel rrangel@chromium.org Change-Id: I8f2035f74240ead4089ff4d503dfbeb447cf8de4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41835 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Furquan Shaikh furquan@google.com --- M src/soc/amd/picasso/acpi/pcie.asl M src/soc/amd/picasso/acpi/sb_fch.asl 2 files changed, 240 insertions(+), 50 deletions(-)
Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved
diff --git a/src/soc/amd/picasso/acpi/pcie.asl b/src/soc/amd/picasso/acpi/pcie.asl index 2bbfec56..561a3f8 100644 --- a/src/soc/amd/picasso/acpi/pcie.asl +++ b/src/soc/amd/picasso/acpi/pcie.asl @@ -16,6 +16,21 @@ PIRG, 0x00000008, /* Index 6: INTG */ PIRH, 0x00000008, /* Index 7: INTH */
+ Offset (0x62), + PGPI, 0x00000008, /* Index 0x62: GPIO */ + + Offset (0x70), + PI20, 0x00000008, /* Index 0x70: I2C0 */ + PI21, 0x00000008, /* Index 0x71: I2C1 */ + PI22, 0x00000008, /* Index 0x72: I2C2 */ + PI23, 0x00000008, /* Index 0x73: I2C3 */ + PUA0, 0x00000008, /* Index 0x74: UART0 */ + PUA1, 0x00000008, /* Index 0x75: UART1 */ + PI24, 0x00000008, /* Index 0x76: I2C4 */ + PI25, 0x00000008, /* Index 0x77: I2C5 */ + PUA2, 0x00000008, /* Index 0x78: UART2 */ + PUA3, 0x00000008, /* Index 0x79: UART3 */ + /* IO-APIC IRQs */ Offset (0x80), IORA, 0x00000008, /* Index 0x80: INTA */ @@ -26,6 +41,21 @@ IORF, 0x00000008, /* Index 0x85: INTF */ IORG, 0x00000008, /* Index 0x86: INTG */ IORH, 0x00000008, /* Index 0x87: INTH */ + + Offset (0xE2), + IGPI, 0x00000008, /* Index 0xE2: GPIO */ + + Offset (0xF0), + II20, 0x00000008, /* Index 0xF0: I2C0 */ + II21, 0x00000008, /* Index 0xF1: I2C1 */ + II22, 0x00000008, /* Index 0xF2: I2C2 */ + II23, 0x00000008, /* Index 0xF3: I2C3 */ + IUA0, 0x00000008, /* Index 0xF4: UART0 */ + IUA1, 0x00000008, /* Index 0xF5: UART1 */ + II24, 0x00000008, /* Index 0xF6: I2C4 */ + II25, 0x00000008, /* Index 0xF7: I2C5 */ + IUA2, 0x00000008, /* Index 0xF8: UART2 */ + IUA3, 0x00000008, /* Index 0xF9: UART3 */ }
/* PCI Error control register */ diff --git a/src/soc/amd/picasso/acpi/sb_fch.asl b/src/soc/amd/picasso/acpi/sb_fch.asl index f8df3c0..c531648 100644 --- a/src/soc/amd/picasso/acpi/sb_fch.asl +++ b/src/soc/amd/picasso/acpi/sb_fch.asl @@ -26,12 +26,30 @@ Name (_UID, 0) Name (_DDN, GPIO_DEVICE_DESC)
- Name (_CRS, ResourceTemplate() - { - Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) - { 7 } - Memory32Fixed (ReadWrite, 0xFED81500, 0x300) - }) + Method (_CRS, 0) { + Name (RBUF, ResourceTemplate() { + Interrupt ( + ResourceConsumer, + Level, + ActiveLow, + Exclusive, , , IRQR) + { 0 } + Memory32Fixed (ReadWrite, 0xFED81500, 0x300) + }) + CreateDWordField (RBUF, IRQR._INT, IRQN) + If (PMOD) { + IRQN = IGPI + } Else { + IRQN = PGPI + } + If (IRQN == 0x1f) { + Return (ResourceTemplate() { + Memory32Fixed (ReadWrite, 0xFED81500, 0x300) + }) + } Else { + Return (RBUF) + } + }
Method (_STA, 0x0, NotSerialized) { @@ -43,12 +61,33 @@ { Name (_HID, "AMD0020") Name (_UID, 0x0) - Name (_CRS, ResourceTemplate() - { - IRQ (Edge, ActiveHigh, Exclusive) { 10 } - Memory32Fixed (ReadWrite, APU_UART0_BASE, 0x1000) - Memory32Fixed (ReadWrite, APU_DMAC0_BASE, 0x1000) - }) + Method (_CRS, 0) { + Name (RBUF, ResourceTemplate() { + Interrupt ( + ResourceConsumer, + Edge, + ActiveHigh, + Exclusive, , , IRQR) + { 0 } + Memory32Fixed (ReadWrite, APU_UART0_BASE, 0x1000) + Memory32Fixed (ReadWrite, APU_DMAC0_BASE, 0x1000) + }) + CreateDWordField (RBUF, IRQR._INT, IRQN) + If (PMOD) { + IRQN = IUA0 + } Else { + IRQN = PUA0 + } + If (IRQN == 0x1f) { + Return (ResourceTemplate() { + Memory32Fixed (ReadWrite, APU_UART0_BASE, 0x1000) + Memory32Fixed (ReadWrite, APU_DMAC0_BASE, 0x1000) + }) + } Else { + Return (RBUF) + } + } + Method (_STA, 0x0, NotSerialized) { Return (0x0F) @@ -58,28 +97,69 @@ Device (FUR1) { Name (_HID, "AMD0020") Name (_UID, 0x1) - Name (_CRS, ResourceTemplate() - { - IRQ (Edge, ActiveHigh, Exclusive) { 11 } - Memory32Fixed (ReadWrite, APU_UART1_BASE, 0x1000) - Memory32Fixed (ReadWrite, APU_DMAC1_BASE, 0x1000) - }) + Method (_CRS, 0) { + Name (RBUF, ResourceTemplate() { + Interrupt ( + ResourceConsumer, + Edge, + ActiveHigh, + Exclusive, , , IRQR) + { 0 } + Memory32Fixed (ReadWrite, APU_UART1_BASE, 0x1000) + Memory32Fixed (ReadWrite, APU_DMAC1_BASE, 0x1000) + }) + CreateDWordField (RBUF, IRQR._INT, IRQN) + If (PMOD) { + IRQN = IUA1 + } Else { + IRQN = PUA1 + } + If (IRQN == 0x1f) { + Return (ResourceTemplate() { + Memory32Fixed (ReadWrite, APU_UART1_BASE, 0x1000) + Memory32Fixed (ReadWrite, APU_DMAC1_BASE, 0x1000) + }) + } Else { + Return (RBUF) + } + } + Method (_STA, 0x0, NotSerialized) { Return (0x0F) } }
-Device (FUR2) -{ +Device (FUR2) { Name (_HID, "AMD0020") - Name (_UID, 0x0) - Name (_CRS, ResourceTemplate() - { - IRQ (Edge, ActiveHigh, Exclusive) { 15 } - Memory32Fixed (ReadWrite, APU_UART2_BASE, 0x1000) - Memory32Fixed (ReadWrite, APU_DMAC2_BASE, 0x1000) - }) + Name (_UID, 0x2) + Method (_CRS, 0) { + Name (RBUF, ResourceTemplate() { + Interrupt ( + ResourceConsumer, + Edge, + ActiveHigh, + Exclusive, , , IRQR) + { 0 } + Memory32Fixed (ReadWrite, APU_UART2_BASE, 0x1000) + Memory32Fixed (ReadWrite, APU_DMAC2_BASE, 0x1000) + }) + CreateDWordField (RBUF, IRQR._INT, IRQN) + If (PMOD) { + IRQN = IUA2 + } Else { + IRQN = PUA2 + } + If (IRQN == 0x1f) { + Return (ResourceTemplate() { + Memory32Fixed (ReadWrite, APU_UART2_BASE, 0x1000) + Memory32Fixed (ReadWrite, APU_DMAC2_BASE, 0x1000) + }) + } Else { + Return (RBUF) + } + } + Method (_STA, 0x0, NotSerialized) { Return (0x0F) @@ -88,13 +168,34 @@
Device (FUR3) { Name (_HID, "AMD0020") - Name (_UID, 0x1) - Name (_CRS, ResourceTemplate() - { - IRQ (Edge, ActiveHigh, Exclusive) { 5 } - Memory32Fixed (ReadWrite, APU_UART3_BASE, 0x1000) - Memory32Fixed (ReadWrite, APU_DMAC3_BASE, 0x1000) - }) + Name (_UID, 0x3) + Method (_CRS, 0) { + Name (RBUF, ResourceTemplate() { + Interrupt ( + ResourceConsumer, + Edge, + ActiveHigh, + Exclusive, , , IRQR) + { 0 } + Memory32Fixed (ReadWrite, APU_UART3_BASE, 0x1000) + Memory32Fixed (ReadWrite, APU_DMAC3_BASE, 0x1000) + }) + CreateDWordField (RBUF, IRQR._INT, IRQN) + If (PMOD) { + IRQN = IUA3 + } Else { + IRQN = PUA3 + } + If (IRQN == 0x1f) { + Return (ResourceTemplate() { + Memory32Fixed (ReadWrite, APU_UART3_BASE, 0x1000) + Memory32Fixed (ReadWrite, APU_DMAC3_BASE, 0x1000) + }) + } Else { + Return (RBUF) + } + } + Method (_STA, 0x0, NotSerialized) { Return (0x0F) @@ -104,11 +205,30 @@ Device (I2C2) { Name (_HID, "AMD0010") Name (_UID, 0x2) - Name (_CRS, ResourceTemplate() - { - IRQ (Edge, ActiveHigh, Exclusive) { 4 } - Memory32Fixed (ReadWrite, APU_I2C2_BASE, 0x1000) - }) + Method (_CRS, 0) { + Name (RBUF, ResourceTemplate() { + Interrupt ( + ResourceConsumer, + Edge, + ActiveHigh, + Exclusive, , , IRQR) + { 0 } + Memory32Fixed (ReadWrite, APU_I2C2_BASE, 0x1000) + }) + CreateDWordField (RBUF, IRQR._INT, IRQN) + If (PMOD) { + IRQN = II22 + } Else { + IRQN = PI22 + } + If (IRQN == 0x1f) { + Return (ResourceTemplate() { + Memory32Fixed (ReadWrite, APU_I2C2_BASE, 0x1000) + }) + } Else { + Return (RBUF) + } + }
Method (_STA, 0x0, NotSerialized) { @@ -120,24 +240,64 @@ { Name (_HID, "AMD0010") Name (_UID, 0x3) - Name (_CRS, ResourceTemplate() { - IRQ (Edge, ActiveHigh, Exclusive) { 6 } - Memory32Fixed(ReadWrite, APU_I2C3_BASE, 0x1000) - }) + Method (_CRS, 0) { + Name (RBUF, ResourceTemplate() { + Interrupt ( + ResourceConsumer, + Edge, + ActiveHigh, + Exclusive, , , IRQR) + { 0 } + Memory32Fixed (ReadWrite, APU_I2C3_BASE, 0x1000) + }) + CreateDWordField (RBUF, IRQR._INT, IRQN) + If (PMOD) { + IRQN = II23 + } Else { + IRQN = PI23 + } + If (IRQN == 0x1f) { + Return (ResourceTemplate() { + Memory32Fixed (ReadWrite, APU_I2C3_BASE, 0x1000) + }) + } Else { + Return (RBUF) + } + } Method (_STA, 0x0, NotSerialized) { Return (0x0F) } }
-Device (I2C4) -{ +Device (I2C4) { Name (_HID, "AMD0010") Name (_UID, 0x4) - Name (_CRS, ResourceTemplate() { - IRQ (Edge, ActiveHigh, Exclusive) { 14 } - Memory32Fixed(ReadWrite, APU_I2C4_BASE, 0x1000) - }) + Method (_CRS, 0) { + Name (RBUF, ResourceTemplate() { + Interrupt ( + ResourceConsumer, + Edge, + ActiveHigh, + Exclusive, , , IRQR) + { 0 } + Memory32Fixed (ReadWrite, APU_I2C4_BASE, 0x1000) + }) + CreateDWordField (RBUF, IRQR._INT, IRQN) + If (PMOD) { + IRQN = II24 + } Else { + IRQN = PI24 + } + If (IRQN == 0x1f) { + Return (ResourceTemplate() { + Memory32Fixed (ReadWrite, APU_I2C4_BASE, 0x1000) + }) + } Else { + Return (RBUF) + } + } + Method (_STA, 0x0, NotSerialized) { Return (0x0F) @@ -149,7 +309,7 @@ Name (_HID, "AMD0040") Name (_UID, 0x3) Name (_CRS, ResourceTemplate() { - Memory32Fixed(ReadWrite, ACPIMMIO_MISC_BASE, 0x100) + Memory32Fixed (ReadWrite, ACPIMMIO_MISC_BASE, 0x100) }) Method (_STA, 0x0, NotSerialized) {
9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41835 )
Change subject: soc/amd/picasso/acpi: Remove hardcoded FCH IRQ numbers ......................................................................
Patch Set 4:
Automatic boot test returned (PASS/FAIL/TOTAL): 4/0/4 Emulation targets: "QEMU x86 q35/ich9" using payload TianoCore : SUCCESS : https://lava.9esec.io/r/4751 "QEMU x86 q35/ich9" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/4750 "QEMU x86 i440fx/piix4" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/4749 "QEMU AArch64" using payload LinuxBoot_u-root_kexec : SUCCESS : https://lava.9esec.io/r/4748
Please note: This test is under development and might not be accurate at all!
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9elements QA (Code Review) -
Furquan Shaikh (Code Review)
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Patrick Georgi (Code Review)
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Raul Rangel (Code Review)