Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80192?usp=email )
Change subject: tree: Use read{64;32;16;8}p and write{64;32;16;8}p ......................................................................
tree: Use read{64;32;16;8}p and write{64;32;16;8}p
Change-Id: Ic596fa01c45d2454999b273fcaad11e3e0733f81 Signed-off-by: Elyes Haouas ehaouas@noos.fr --- M src/arch/riscv/arch_timer.c M src/device/oprom/realmode/x86.c M src/mainboard/emulation/qemu-riscv/clint.c M src/mainboard/emulation/spike-riscv/clint.c M src/mainboard/google/mistral/mainboard.c M src/mainboard/protectli/vault_cml/mainboard.c M src/mainboard/siemens/fa_ehl/romstage_fsp_params.c M src/mainboard/siemens/mc_ehl/romstage_fsp_params.c M src/security/intel/txt/common.c M src/security/intel/txt/logging.c M src/security/intel/txt/ramstage.c M src/security/intel/txt/romstage.c M src/security/intel/txt/txtlib.c M src/soc/amd/genoa_poc/uart.c M src/soc/intel/braswell/gpio.c M src/soc/intel/braswell/lpc_init.c M src/soc/intel/braswell/lpe.c M src/soc/intel/braswell/southcluster.c M src/soc/intel/denverton_ns/acpi.c M src/soc/intel/denverton_ns/bootblock/uart.c M src/soc/intel/denverton_ns/gpio_dnv.c M src/soc/intel/denverton_ns/lpc.c M src/soc/intel/denverton_ns/romstage.c M src/soc/intel/denverton_ns/sata.c M src/soc/intel/meteorlake/crashlog.c M src/soc/intel/xeon_sp/spr/soc_acpi.c M src/soc/mediatek/common/tracker.c M src/soc/mediatek/common/tracker_v2.c M src/soc/mediatek/common/ufs.c M src/soc/mediatek/mt8183/ddp.c M src/soc/mediatek/mt8186/ddp.c M src/soc/mediatek/mt8186/gic.c M src/soc/mediatek/mt8186/spm.c M src/soc/mediatek/mt8192/ddp.c M src/soc/mediatek/mt8195/apusys_devapc.c M src/soc/mediatek/mt8195/ddp.c M src/soc/mediatek/mt8195/hdmi.c M src/soc/mediatek/mt8195/usb.c M src/soc/nvidia/tegra/apbmisc.c M src/soc/nvidia/tegra124/monotonic_timer.c M src/soc/nvidia/tegra210/bootblock.c M src/soc/nvidia/tegra210/clock.c M src/soc/nvidia/tegra210/i2c6.c M src/soc/nvidia/tegra210/monotonic_timer.c M src/soc/nvidia/tegra210/ramstage.c M src/soc/qualcomm/common/qupv3_config.c M src/soc/qualcomm/sc7280/socinfo.c M src/soc/samsung/exynos5250/cpu.c M src/soc/samsung/exynos5420/cpu.c M src/soc/samsung/exynos5420/dp_lowlevel.c M src/soc/samsung/exynos5420/fimd.c M src/soc/samsung/exynos5420/smp.c M src/soc/sifive/fu540/clint.c 53 files changed, 202 insertions(+), 195 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/80192/1
diff --git a/src/arch/riscv/arch_timer.c b/src/arch/riscv/arch_timer.c index ad678b7..6738751 100644 --- a/src/arch/riscv/arch_timer.c +++ b/src/arch/riscv/arch_timer.c @@ -10,5 +10,5 @@ { if (HLS()->time == NULL) die("time not set in HLS"); - mono_time_set_usecs(mt, (long)read64((void *)(HLS()->time))); + mono_time_set_usecs(mt, (long)read64p((HLS()->time))); } diff --git a/src/device/oprom/realmode/x86.c b/src/device/oprom/realmode/x86.c index 367614d..dafb949 100644 --- a/src/device/oprom/realmode/x86.c +++ b/src/device/oprom/realmode/x86.c @@ -72,7 +72,7 @@ memcpy((void *)0xfffd9, &ident, 7);
/* system model: IBM-AT */ - write8((void *)0xffffe, 0xfc); + write8p(0xffffe, 0xfc); }
static int (*intXX_handler[256])(void) = { NULL }; diff --git a/src/mainboard/emulation/qemu-riscv/clint.c b/src/mainboard/emulation/qemu-riscv/clint.c index 10827fa..3436568 100644 --- a/src/mainboard/emulation/qemu-riscv/clint.c +++ b/src/mainboard/emulation/qemu-riscv/clint.c @@ -14,5 +14,5 @@
void set_msip(int hartid, int val) { - write32((void *)(QEMU_VIRT_CLINT + 4 * (uintptr_t)hartid), !!val); + write32p((QEMU_VIRT_CLINT + 4 * (uintptr_t)hartid), !!val); } diff --git a/src/mainboard/emulation/spike-riscv/clint.c b/src/mainboard/emulation/spike-riscv/clint.c index 4d45bce..f510e0b 100644 --- a/src/mainboard/emulation/spike-riscv/clint.c +++ b/src/mainboard/emulation/spike-riscv/clint.c @@ -15,5 +15,5 @@
void set_msip(int hartid, int val) { - write32((void *)(SPIKE_CLINT_BASE + 4 * (uintptr_t)hartid), !!val); + write32p((SPIKE_CLINT_BASE + 4 * (uintptr_t)hartid), !!val); } diff --git a/src/mainboard/google/mistral/mainboard.c b/src/mainboard/google/mistral/mainboard.c index e45ff8f..0dd1360 100644 --- a/src/mainboard/google/mistral/mainboard.c +++ b/src/mainboard/google/mistral/mainboard.c @@ -22,7 +22,7 @@ static void configure_sdhci(void) { /* Program eMMC drive strength to 16/10/10 mA */ - write32((void *)SDC1_TLMM_CFG_ADDR, 0x9FE4); + write32p(SDC1_TLMM_CFG_ADDR, 0x9FE4); }
static void mainboard_init(struct device *dev) diff --git a/src/mainboard/protectli/vault_cml/mainboard.c b/src/mainboard/protectli/vault_cml/mainboard.c index 1e06fc5..515cb70 100644 --- a/src/mainboard/protectli/vault_cml/mainboard.c +++ b/src/mainboard/protectli/vault_cml/mainboard.c @@ -51,14 +51,14 @@ static bool is_descriptor_writeable(uint8_t *desc) { /* Check flash has valid signature */ - if (read32((void *)(desc + FLASH_SIGNATURE_OFFSET)) != FLASH_SIGNATURE_VAL) { + if (read32p((desc + FLASH_SIGNATURE_OFFSET)) != FLASH_SIGNATURE_VAL) { printk(BIOS_ERR, "Flash Descriptor is not valid\n"); printk(BIOS_ERR, "Descriptor needs to be fixed to ensure proper operation\n"); return false; }
/* Check host has write access to the Descriptor Region */ - if (!((read32((void *)(desc + FLMSTR1)) >> FLMSTR_WR_SHIFT_V2) & BIT(0))) { + if (!((read32p((desc + FLMSTR1)) >> FLMSTR_WR_SHIFT_V2) & BIT(0))) { printk(BIOS_ERR, "Host doesn't have write access to Descriptor Region\n"); return false; } diff --git a/src/mainboard/siemens/fa_ehl/romstage_fsp_params.c b/src/mainboard/siemens/fa_ehl/romstage_fsp_params.c index 506bcc6..7337e27 100644 --- a/src/mainboard/siemens/fa_ehl/romstage_fsp_params.c +++ b/src/mainboard/siemens/fa_ehl/romstage_fsp_params.c @@ -22,7 +22,7 @@ memset(spd_data, 0, sizeof(spd_data)); if ((hwilib_find_blocks(cbfs_hwi_name) == CB_SUCCESS) && (hwilib_get_field(SPD, spd_data, 0x80) == 0x80) && - (ddr_crc16(spd_data, 126) == read16((void *)&spd_data[126]))) { + (ddr_crc16(spd_data, 126) == read16p(&spd_data[126]))) { spd_info.spd_spec.spd_data_ptr_info.spd_data_ptr = (uintptr_t)spd_data; spd_info.spd_spec.spd_data_ptr_info.spd_data_len = CONFIG_DIMM_SPD_SIZE; spd_info.read_type = READ_SPD_MEMPTR; diff --git a/src/mainboard/siemens/mc_ehl/romstage_fsp_params.c b/src/mainboard/siemens/mc_ehl/romstage_fsp_params.c index d386d75..b74a60e 100644 --- a/src/mainboard/siemens/mc_ehl/romstage_fsp_params.c +++ b/src/mainboard/siemens/mc_ehl/romstage_fsp_params.c @@ -26,7 +26,7 @@ memset(spd_data, 0, sizeof(spd_data)); if ((hwilib_find_blocks(cbfs_hwi_name) == CB_SUCCESS) && (hwilib_get_field(SPD, spd_data, 0x80) == 0x80) && - (ddr_crc16(spd_data, 126) == read16((void *)&spd_data[126]))) { + (ddr_crc16(spd_data, 126) == read16p(&spd_data[126]))) { spd_info.spd_spec.spd_data_ptr_info.spd_data_ptr = (uintptr_t)spd_data; spd_info.spd_spec.spd_data_ptr_info.spd_data_len = CONFIG_DIMM_SPD_SIZE; spd_info.read_type = READ_SPD_MEMPTR; diff --git a/src/security/intel/txt/common.c b/src/security/intel/txt/common.c index b78394a..6fba958 100644 --- a/src/security/intel/txt/common.c +++ b/src/security/intel/txt/common.c @@ -100,7 +100,7 @@
void intel_txt_log_spad(void) { - const uint64_t acm_status = read64((void *)TXT_SPAD); + const uint64_t acm_status = read64p(TXT_SPAD);
printk(BIOS_INFO, "TXT-STS: ACM verification ");
@@ -138,8 +138,8 @@ if (!CONFIG(INTEL_TXT)) return false;
- ret = (read8((void *)TXT_ESTS) & TXT_ESTS_WAKE_ERROR_STS) || - (read64((void *)TXT_E2STS) & TXT_E2STS_SECRET_STS); + ret = (read8p(TXT_ESTS) & TXT_ESTS_WAKE_ERROR_STS) || + (read64p(TXT_E2STS) & TXT_E2STS_SECRET_STS);
if (ret) printk(BIOS_CRIT, "TXT-STS: Secrets in memory!\n"); @@ -154,10 +154,10 @@ * Chapter B.1.7 and B.1.9 * Intel TXT Software Development Guide (Document: 315168-015) */ - uint32_t reg = read32((void *)TXT_VER_FSBIF); + uint32_t reg = read32p(TXT_VER_FSBIF);
if (reg == 0 || reg == UINT32_MAX) - reg = read32((void *)TXT_VER_QPIIF); + reg = read32p(TXT_VER_QPIIF);
return (reg & TXT_VER_PRODUCTION_FUSED) ? true : false; } @@ -320,11 +320,11 @@ return;
/* FIXME: Do we need to program these two? */ - //write32((void *)MCU_BASE_ADDR, 0xffe1a990); - //write32((void *)APINIT_ADDR, 0xfffffff0); + //write32p(MCU_BASE_ADDR, 0xffe1a990); + //write32p(APINIT_ADDR, 0xfffffff0);
- write32((void *)BIOACM_ADDR, (uintptr_t)acm_data); - write32((void *)SEMAPHORE, 0); + write32p(BIOACM_ADDR, (uintptr_t)acm_data); + write32p(SEMAPHORE, 0);
/* * The time SCLEAN will take depends on the installed RAM size. @@ -364,14 +364,14 @@
cbfs_unmap(acm_data);
- const uint64_t acm_status = read64((void *)TXT_SPAD); + const uint64_t acm_status = read64p(TXT_SPAD); if (acm_status & ACMERROR_TXT_VALID) { printk(BIOS_ERR, "TEE-TXT: FATAL ACM launch error !\n"); /* * WARNING ! * To clear TXT.BIOSACM.ERRORCODE you must issue a cold reboot! */ - intel_txt_log_acm_error(read32((void *)TXT_BIOSACM_ERRORCODE)); + intel_txt_log_acm_error(read32p(TXT_BIOSACM_ERRORCODE)); return -1; }
@@ -460,7 +460,7 @@ if ((eax & 0x7d) != 0x7d) failure = true;
- const uint64_t status = read64((void *)TXT_SPAD); + const uint64_t status = read64p(TXT_SPAD);
if (status & ACMSTS_TXT_DISABLED) { printk(BIOS_INFO, "TEE-TXT: TXT disabled by BIOS policy in FIT.\n"); diff --git a/src/security/intel/txt/logging.c b/src/security/intel/txt/logging.c index 6485b86..e1692cf 100644 --- a/src/security/intel/txt/logging.c +++ b/src/security/intel/txt/logging.c @@ -35,7 +35,7 @@ */ static void log_txt_error(const char *phase) { - const uint64_t txt_error = read64((void *)TXT_ERROR); + const uint64_t txt_error = read64p(TXT_ERROR);
if (txt_error & ACMERROR_TXT_VALID) { printk(BIOS_ERR, "%s: Error occurred\n", phase); @@ -63,9 +63,9 @@
printk(BIOS_INFO, "TEE-TXT: State of ACM and ucode update:\n");
- bios_acm_error = read32((void *)TXT_BIOSACM_ERRORCODE); - acm_status = read64((void *)TXT_SPAD); - txt_error = read64((void *)TXT_ERROR); + bios_acm_error = read32p(TXT_BIOSACM_ERRORCODE); + acm_status = read64p(TXT_SPAD); + txt_error = read64p(TXT_ERROR);
/* Errors by BIOS ACM or FIT */ if ((txt_error & ACMERROR_TXT_VALID) && @@ -81,10 +81,10 @@ }
/* Check for fatal ACM error and TXT reset */ - uint8_t error = read8((void *)TXT_ESTS); + uint8_t error = read8p(TXT_ESTS); if (error & TXT_ESTS_TXT_RESET_STS) { printk(BIOS_CRIT, "TXT-STS: Intel TXT reset detected\n"); - intel_txt_log_acm_error(read32((void *)TXT_ERROR)); + intel_txt_log_acm_error(read32p(TXT_ERROR)); } }
@@ -178,12 +178,12 @@ { printk(BIOS_INFO, "TEE-TXT: Chipset Key Hash 0x"); for (int i = 0; i < TXT_ACM_KEY_HASH_LEN; i++) { - printk(BIOS_INFO, "%llx", read64((void *)TXT_ACM_KEY_HASH + + printk(BIOS_INFO, "%llx", read64p(TXT_ACM_KEY_HASH + (i * sizeof(uint64_t)))); } printk(BIOS_INFO, "\n");
- printk(BIOS_INFO, "TEE-TXT: DIDVID 0x%x\n", read32((void *)TXT_DIDVID)); + printk(BIOS_INFO, "TEE-TXT: DIDVID 0x%x\n", read32p(TXT_DIDVID)); printk(BIOS_INFO, "TEE-TXT: production fused chipset: %s\n", intel_txt_chipset_is_production_fused() ? "true" : "false"); } @@ -199,18 +199,18 @@
uint64_t reg64;
- reg64 = read64((void *)TXT_HEAP_BASE); + reg64 = read64p(TXT_HEAP_BASE); if ((reg64 != 0 && reg64 != ~0UL) && - (read64((void *)(uintptr_t)reg64) >= (sizeof(*bdr) + sizeof(uint64_t)))) + (read64p((uintptr_t)reg64) >= (sizeof(*bdr) + sizeof(uint64_t)))) bdr = (void *)((uintptr_t)reg64 + sizeof(uint64_t));
printk(BIOS_DEBUG, "TEE-TXT: TSEG 0x%lx, size %zu MiB\n", tseg_base, tseg_size / MiB); - printk(BIOS_DEBUG, "TEE-TXT: TXT.HEAP.BASE 0x%llx\n", read64((void *)TXT_HEAP_BASE)); - printk(BIOS_DEBUG, "TEE-TXT: TXT.HEAP.SIZE 0x%llx\n", read64((void *)TXT_HEAP_SIZE)); - printk(BIOS_DEBUG, "TEE-TXT: TXT.SINIT.BASE 0x%llx\n", read64((void *)TXT_SINIT_BASE)); - printk(BIOS_DEBUG, "TEE-TXT: TXT.SINIT.SIZE 0x%llx\n", read64((void *)TXT_SINIT_SIZE)); - printk(BIOS_DEBUG, "TEE-TXT: TXT.MSEG.BASE 0x%llx\n", read64((void *)TXT_MSEG_BASE)); - printk(BIOS_DEBUG, "TEE-TXT: TXT.MSEG.SIZE 0x%llx\n", read64((void *)TXT_MSEG_SIZE)); + printk(BIOS_DEBUG, "TEE-TXT: TXT.HEAP.BASE 0x%llx\n", read64p(TXT_HEAP_BASE)); + printk(BIOS_DEBUG, "TEE-TXT: TXT.HEAP.SIZE 0x%llx\n", read64p(TXT_HEAP_SIZE)); + printk(BIOS_DEBUG, "TEE-TXT: TXT.SINIT.BASE 0x%llx\n", read64p(TXT_SINIT_BASE)); + printk(BIOS_DEBUG, "TEE-TXT: TXT.SINIT.SIZE 0x%llx\n", read64p(TXT_SINIT_SIZE)); + printk(BIOS_DEBUG, "TEE-TXT: TXT.MSEG.BASE 0x%llx\n", read64p(TXT_MSEG_BASE)); + printk(BIOS_DEBUG, "TEE-TXT: TXT.MSEG.SIZE 0x%llx\n", read64p(TXT_MSEG_SIZE));
if (bdr) { printk(BIOS_DEBUG, "TEE-TXT: BiosDataRegion.bios_sinit_size 0x%x\n", diff --git a/src/security/intel/txt/ramstage.c b/src/security/intel/txt/ramstage.c index 8a266a4..5c03da9 100644 --- a/src/security/intel/txt/ramstage.c +++ b/src/security/intel/txt/ramstage.c @@ -20,8 +20,8 @@ /* FIXME: Seems to work only on some platforms */ static void log_ibb_measurements(void) { - const uint64_t mseg_size = read64((void *)TXT_MSEG_SIZE); - uint64_t mseg_base = read64((void *)TXT_MSEG_BASE); + const uint64_t mseg_size = read64p(TXT_MSEG_SIZE); + uint64_t mseg_base = read64p(TXT_MSEG_BASE);
if (!mseg_size || !mseg_base || mseg_size <= mseg_base) return; @@ -34,14 +34,14 @@
printk(BIOS_INFO, "TEE-TXT: IBB Hash 0x"); for (; mseg_base < mseg_size; mseg_base++) - printk(BIOS_INFO, "%02X", read8((void *)(uintptr_t)mseg_base)); + printk(BIOS_INFO, "%02X", read8p((uintptr_t)mseg_base));
printk(BIOS_INFO, "\n"); }
void bootmem_platform_add_ranges(void) { - uint64_t status = read64((void *)TXT_SPAD); + uint64_t status = read64p(TXT_SPAD);
if (status & ACMSTS_TXT_DISABLED) return; @@ -67,7 +67,7 @@ BM_MEM_RESERVED);
const union dpr_register dpr = { - .raw = read32((void *)TXT_DPR), + .raw = read32p(TXT_DPR), };
const uint32_t dpr_base = dpr.top - dpr.size * MiB; @@ -78,13 +78,13 @@
static bool get_wake_error_status(void) { - const uint8_t error = read8((void *)TXT_ESTS); + const uint8_t error = read8p(TXT_ESTS); return !!(error & TXT_ESTS_WAKE_ERROR_STS); }
static void check_secrets_txt(void *unused) { - uint64_t status = read64((void *)TXT_SPAD); + uint64_t status = read64p(TXT_SPAD);
if (status & ACMSTS_TXT_DISABLED) return; @@ -102,7 +102,7 @@ intel_txt_run_bios_acm(ACMINPUT_CLEAR_SECRETS);
/* Should never reach this point ... */ - intel_txt_log_acm_error(read32((void *)TXT_BIOSACM_ERRORCODE)); + intel_txt_log_acm_error(read32p(TXT_BIOSACM_ERRORCODE)); die("Waiting for platform reset...\n"); } } @@ -121,7 +121,7 @@ */ static void init_intel_txt(void *unused) { - const uint64_t status = read64((void *)TXT_SPAD); + const uint64_t status = read64p(TXT_SPAD);
if (status & ACMSTS_TXT_DISABLED) return; @@ -250,10 +250,10 @@ txt_heap_fill_common_bdr(&data.bdr); txt_heap_fill_bios_spec(&data.spec);
- void *sinit_base = (void *)(uintptr_t)read64((void *)TXT_SINIT_BASE); + void *sinit_base = (void *)(uintptr_t)read64p(TXT_SINIT_BASE); data.bdr.bios_sinit_size = cbfs_load(CONFIG_INTEL_TXT_CBFS_SINIT_ACM, sinit_base, - read64((void *)TXT_SINIT_SIZE)); + read64p(TXT_SINIT_SIZE));
/* Extended elements - ACM addresses */ data.heap_acm.header.type = HEAP_EXTDATA_TYPE_ACM; @@ -295,9 +295,9 @@ txt_heap_fill_common_bdr(&data.bdr); txt_heap_fill_bios_spec(&data.spec);
- void *sinit_base = (void *)(uintptr_t)read64((void *)TXT_SINIT_BASE); + void *sinit_base = (void *)(uintptr_t)read64p(TXT_SINIT_BASE); /* Clear SINIT ACM memory */ - memset(sinit_base, 0, read64((void *)TXT_SINIT_SIZE)); + memset(sinit_base, 0, read64p(TXT_SINIT_SIZE));
/* Extended elements - ACM addresses */ data.heap_acm.header.type = HEAP_EXTDATA_TYPE_ACM; @@ -318,7 +318,7 @@ static void txt_initialize_heap(void) { /* Fill TXT.HEAP.BASE with 4 subregions */ - u8 *heap_struct = (void *)((uintptr_t)read64((void *)TXT_HEAP_BASE)); + u8 *heap_struct = (void *)((uintptr_t)read64p(TXT_HEAP_BASE));
/* * Since we may have either BIOS ACM or both BIOS and SINIT ACMs in @@ -365,7 +365,7 @@ if (skip_intel_txt_lockdown()) return;
- const uint64_t status = read64((void *)TXT_SPAD); + const uint64_t status = read64p(TXT_SPAD);
uint32_t txt_feature_flags = 0; uintptr_t tseg_base; @@ -401,7 +401,7 @@ * Chapter 5.5.6.1 DMA Protection Memory Region */
- const u8 dpr_capable = !!(read64((void *)TXT_CAPABILITIES) & + const u8 dpr_capable = !!(read64p(TXT_CAPABILITIES) & TXT_CAPABILITIES_DPR); printk(BIOS_INFO, "TEE-TXT: DPR capable %x\n", dpr_capable);
@@ -443,28 +443,28 @@ dpr.prs = 0; dpr.epm = 0;
- write64((void *)TXT_DPR, dpr.raw); + write64p(TXT_DPR, dpr.raw);
printk(BIOS_INFO, "TEE-TXT: TXT.DPR 0x%08x\n", - read32((void *)TXT_DPR)); + read32p(TXT_DPR)); }
/* * Document Number: 558294 * Chapter 5.5.6.3 Intel TXT Heap Memory Region */ - write64((void *)TXT_HEAP_SIZE, CONFIG_INTEL_TXT_HEAP_SIZE); - write64((void *)TXT_HEAP_BASE, - ALIGN_DOWN(tseg_base - read64((void *)TXT_HEAP_SIZE), 4096)); + write64p(TXT_HEAP_SIZE, CONFIG_INTEL_TXT_HEAP_SIZE); + write64p(TXT_HEAP_BASE, + ALIGN_DOWN(tseg_base - read64p(TXT_HEAP_SIZE), 4096));
/* * Document Number: 558294 * Chapter 5.5.6.2 SINIT Memory Region */ - write64((void *)TXT_SINIT_SIZE, CONFIG_INTEL_TXT_SINIT_SIZE); - write64((void *)TXT_SINIT_BASE, - ALIGN_DOWN(read64((void *)TXT_HEAP_BASE) - - read64((void *)TXT_SINIT_SIZE), 4096)); + write64p(TXT_SINIT_SIZE, CONFIG_INTEL_TXT_SINIT_SIZE); + write64p(TXT_SINIT_BASE, + ALIGN_DOWN(read64p(TXT_HEAP_BASE) - + read64p(TXT_SINIT_SIZE), 4096));
/* * FIXME: Server-TXT capable platforms need to install an STM in SMM and set up MSEG. @@ -474,8 +474,8 @@ * Chapter 5.10.1 SMM in the Intel TXT for Servers Environment * Disable MSEG. */ - write64((void *)TXT_MSEG_SIZE, 0); - write64((void *)TXT_MSEG_BASE, 0); + write64p(TXT_MSEG_SIZE, 0); + write64p(TXT_MSEG_BASE, 0);
/* Only initialize the heap on regular boots */ if (!acpi_is_wakeup_s3()) diff --git a/src/security/intel/txt/romstage.c b/src/security/intel/txt/romstage.c index aa7cc2c..643e7a9 100644 --- a/src/security/intel/txt/romstage.c +++ b/src/security/intel/txt/romstage.c @@ -63,7 +63,7 @@ return; }
- const uint8_t txt_ests = read8((void *)TXT_ESTS); + const uint8_t txt_ests = read8p(TXT_ESTS);
const bool establishment = is_establishment_bit_asserted(); const bool is_wake_error = !!(txt_ests & TXT_ESTS_WAKE_ERROR_STS); diff --git a/src/security/intel/txt/txtlib.c b/src/security/intel/txt/txtlib.c index 5478206..6ce86a3 100644 --- a/src/security/intel/txt/txtlib.c +++ b/src/security/intel/txt/txtlib.c @@ -20,7 +20,7 @@ stopwatch_init_msecs_expire(&timer, 50);
while (true) { - access = read8((void *)TPM_ACCESS_REG); + access = read8p(TPM_ACCESS_REG);
/* Register returns all ones if TPM is missing */ if (access == 0xff) diff --git a/src/soc/amd/genoa_poc/uart.c b/src/soc/amd/genoa_poc/uart.c index df8c54f..ffc5668 100644 --- a/src/soc/amd/genoa_poc/uart.c +++ b/src/soc/amd/genoa_poc/uart.c @@ -34,5 +34,5 @@
void clear_uart_legacy_config(void) { - write16((void *)FCH_LEGACY_UART_DECODE, 0); + write16p(FCH_LEGACY_UART_DECODE, 0); } diff --git a/src/soc/intel/braswell/gpio.c b/src/soc/intel/braswell/gpio.c index 58970e83..ec2a54c 100644 --- a/src/soc/intel/braswell/gpio.c +++ b/src/soc/intel/braswell/gpio.c @@ -204,8 +204,8 @@ community->gpio_to_pad[gpio], gpio); #endif /* Write pad configurations to conf0 and conf1 register */ - write32((void *)(reg + PAD_CONF0_REG), config->pad_conf0); - write32((void *)(reg + PAD_CONF1_REG), config->pad_conf1); + write32p((reg + PAD_CONF0_REG), config->pad_conf0); + write32p((reg + PAD_CONF1_REG), config->pad_conf1); } }
@@ -215,14 +215,14 @@ #endif
/* Wake */ - write32((void *)(community->pad_base + GPIO_WAKE_MASK_REG0), gpio_wake0); + write32p((community->pad_base + GPIO_WAKE_MASK_REG0), gpio_wake0);
/* Wake mask config for communities with 2 regs */ if (community->gpio_count > 32) - write32((void *)(community->pad_base + GPIO_WAKE_MASK_REG1), gpio_wake1); + write32p((community->pad_base + GPIO_WAKE_MASK_REG1), gpio_wake1);
/* Interrupt */ - write32((void *)(community->pad_base + GPIO_INTERRUPT_MASK), gpio_int_mask); + write32p((community->pad_base + GPIO_INTERRUPT_MASK), gpio_int_mask); }
void setup_soc_gpios(struct soc_gpio_config *config, u8 enable_xdp_tap) @@ -233,7 +233,7 @@ * Write the default value 0xffffff to the SW write_access_policy_interrupt_reg * to allow the SW interrupt mask register to be set */ - write32((void *)(COMMUNITY_GPSOUTHWEST_BASE + 0x108), 0xffffffff); + write32p((COMMUNITY_GPSOUTHWEST_BASE + 0x108), 0xffffffff);
printk(BIOS_DEBUG, "north\n"); setup_gpios(config->north, &gpnorth_community); diff --git a/src/soc/intel/braswell/lpc_init.c b/src/soc/intel/braswell/lpc_init.c index d476d5d..15a17b7 100644 --- a/src/soc/intel/braswell/lpc_init.c +++ b/src/soc/intel/braswell/lpc_init.c @@ -37,41 +37,41 @@ static void lpc_gpio_config(u32 cycle) { if (cycle == SUSPEND_CYCLE) { /* Suspend cycle */ - write32((void *)(COMMUNITY_GPSOUTHEAST_BASE + LPC_FRAME_MMIO_OFFSET), + write32p((COMMUNITY_GPSOUTHEAST_BASE + LPC_FRAME_MMIO_OFFSET), PAD_CFG0_NATIVE_PU20K(1));
- write32((void *)(COMMUNITY_GPSOUTHEAST_BASE + LPC_AD0_MMIO_OFFSET), + write32p((COMMUNITY_GPSOUTHEAST_BASE + LPC_AD0_MMIO_OFFSET), PAD_CFG0_NATIVE_PU20K(1));
- write32((void *)(COMMUNITY_GPSOUTHEAST_BASE + LPC_AD1_MMIO_OFFSET), + write32p((COMMUNITY_GPSOUTHEAST_BASE + LPC_AD1_MMIO_OFFSET), PAD_CFG0_NATIVE_PU20K(1));
- write32((void *)(COMMUNITY_GPSOUTHEAST_BASE + LPC_AD2_MMIO_OFFSET), + write32p((COMMUNITY_GPSOUTHEAST_BASE + LPC_AD2_MMIO_OFFSET), PAD_CFG0_NATIVE_PU20K(1));
- write32((void *)(COMMUNITY_GPSOUTHEAST_BASE + LPC_AD3_MMIO_OFFSET), + write32p((COMMUNITY_GPSOUTHEAST_BASE + LPC_AD3_MMIO_OFFSET), PAD_CFG0_NATIVE_PU20K(1));
- write32((void *)(COMMUNITY_GPSOUTHEAST_BASE + LPC_CLKRUN_MMIO_OFFSET), + write32p((COMMUNITY_GPSOUTHEAST_BASE + LPC_CLKRUN_MMIO_OFFSET), PAD_CFG0_NATIVE_PD20K(1));
} else { /* Resume cycle */ - write32((void *)(COMMUNITY_GPSOUTHEAST_BASE + LPC_FRAME_MMIO_OFFSET), + write32p((COMMUNITY_GPSOUTHEAST_BASE + LPC_FRAME_MMIO_OFFSET), PAD_CFG0_NATIVE_M1);
- write32((void *)(COMMUNITY_GPSOUTHEAST_BASE + LPC_AD0_MMIO_OFFSET), + write32p((COMMUNITY_GPSOUTHEAST_BASE + LPC_AD0_MMIO_OFFSET), PAD_CFG0_NATIVE_PU20K(1));
- write32((void *)(COMMUNITY_GPSOUTHEAST_BASE + LPC_AD1_MMIO_OFFSET), + write32p((COMMUNITY_GPSOUTHEAST_BASE + LPC_AD1_MMIO_OFFSET), PAD_CFG0_NATIVE_PU20K(1));
- write32((void *)(COMMUNITY_GPSOUTHEAST_BASE + LPC_AD2_MMIO_OFFSET), + write32p((COMMUNITY_GPSOUTHEAST_BASE + LPC_AD2_MMIO_OFFSET), PAD_CFG0_NATIVE_PU20K(1));
- write32((void *)(COMMUNITY_GPSOUTHEAST_BASE + LPC_AD3_MMIO_OFFSET), + write32p((COMMUNITY_GPSOUTHEAST_BASE + LPC_AD3_MMIO_OFFSET), PAD_CFG0_NATIVE_PU20K(1));
- write32((void *)(COMMUNITY_GPSOUTHEAST_BASE + LPC_CLKRUN_MMIO_OFFSET), + write32p((COMMUNITY_GPSOUTHEAST_BASE + LPC_CLKRUN_MMIO_OFFSET), PAD_CFG0_NATIVE_M1); } } diff --git a/src/soc/intel/braswell/lpe.c b/src/soc/intel/braswell/lpe.c index 92632d8..d776c6a 100644 --- a/src/soc/intel/braswell/lpe.c +++ b/src/soc/intel/braswell/lpe.c @@ -122,8 +122,8 @@
/* Also put the address in MMIO space like on C0 BTM */ mmio = find_resource(dev, PCI_BASE_ADDRESS_0); - write32((void *)(uintptr_t)(mmio->base + FIRMWARE_REG_BASE_C0), res->base); - write32((void *)(uintptr_t)(mmio->base + FIRMWARE_REG_LENGTH_C0), res->size); + write32p((uintptr_t)(mmio->base + FIRMWARE_REG_BASE_C0), res->base); + write32p((uintptr_t)(mmio->base + FIRMWARE_REG_LENGTH_C0), res->size); }
static void lpe_init(struct device *dev) diff --git a/src/soc/intel/braswell/southcluster.c b/src/soc/intel/braswell/southcluster.c index a0df97c..caa62bc 100644 --- a/src/soc/intel/braswell/southcluster.c +++ b/src/soc/intel/braswell/southcluster.c @@ -248,7 +248,7 @@ PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL);
/* Use IRQ9 for SCI Interrupt */ - write32((void *)(ilb_base + ACTL), 0); + write32p((ilb_base + ACTL), 0);
isa_dma_init();
@@ -256,11 +256,11 @@
/* Set up the PIRQ PIC routing based on static config. */ for (i = 0; i < NUM_PIRQS; i++) - write8((void *)(pr_base + i*sizeof(ir->pic[i])), ir->pic[i]); + write8p((pr_base + i*sizeof(ir->pic[i])), ir->pic[i]);
/* Set up the per device PIRQ routing base on static config. */ for (i = 0; i < NUM_IR_DEVS; i++) - write16((void *)(ir_base + i*sizeof(ir->pcidev[i])), ir->pcidev[i]); + write16p((ir_base + i*sizeof(ir->pcidev[i])), ir->pcidev[i]);
/* Interrupt 9 should be level triggered (SCI) */ i8259_configure_irq_trigger(9, 1); diff --git a/src/soc/intel/denverton_ns/acpi.c b/src/soc/intel/denverton_ns/acpi.c index d0fde3e..7cabcf64 100644 --- a/src/soc/intel/denverton_ns/acpi.c +++ b/src/soc/intel/denverton_ns/acpi.c @@ -8,6 +8,7 @@ #include <cpu/cpu.h> #include <cpu/x86/smm.h> #include <string.h> +#include <device/mmio.h> #include <device/pci.h> #include <device/pci_ops.h> #include <cbmem.h> @@ -168,7 +169,7 @@ uint64_t vtbar; unsigned long tmp = current;
- vtbar = read64((void *)(DEFAULT_MCHBAR + MCH_VTBAR_OFFSET)) & MCH_VTBAR_MASK; + vtbar = read64p((DEFAULT_MCHBAR + MCH_VTBAR_OFFSET)) & MCH_VTBAR_MASK; printk(BIOS_DEBUG, "DEFVTBAR:0x%llx\n", vtbar); if (!vtbar) return current; diff --git a/src/soc/intel/denverton_ns/bootblock/uart.c b/src/soc/intel/denverton_ns/bootblock/uart.c index ea99051..c85a157 100644 --- a/src/soc/intel/denverton_ns/bootblock/uart.c +++ b/src/soc/intel/denverton_ns/bootblock/uart.c @@ -65,7 +65,7 @@ reg32 &= ~B_PCH_GPIO_PAD_MODE; reg32 |= (UINT32)(V_PCH_GPIO_PAD_MODE_NAT_1 << N_PCH_GPIO_PAD_MODE); - write32((void *)PCH_PCR_ADDRESS(PID_GPIOCOM1, + write32p(PCH_PCR_ADDRESS(PID_GPIOCOM1, R_PAD_CFG_DW0_UART0_RXD), reg32); } @@ -77,31 +77,31 @@ reg32 &= ~B_PCH_GPIO_PAD_MODE; reg32 |= (UINT32)(V_PCH_GPIO_PAD_MODE_NAT_1 << N_PCH_GPIO_PAD_MODE); - write32((void *)PCH_PCR_ADDRESS(PID_GPIOCOM1, + write32p(PCH_PCR_ADDRESS(PID_GPIOCOM1, R_PAD_CFG_DW0_UART0_TXD), reg32); } // UART0_CTS - reg32 = read32((void *)PCH_PCR_ADDRESS(PID_GPIOCOM1, + reg32 = read32p(PCH_PCR_ADDRESS(PID_GPIOCOM1, R_PAD_CFG_DW0_SMB3_CLTT_CLK)); if (((reg32 & B_PCH_GPIO_PAD_MODE) >> N_PCH_GPIO_PAD_MODE) != V_PCH_GPIO_PAD_MODE_NAT_2) { reg32 &= ~B_PCH_GPIO_PAD_MODE; reg32 |= (UINT32)(V_PCH_GPIO_PAD_MODE_NAT_2 << N_PCH_GPIO_PAD_MODE); - write32((void *)PCH_PCR_ADDRESS(PID_GPIOCOM1, + write32p(PCH_PCR_ADDRESS(PID_GPIOCOM1, R_PAD_CFG_DW0_SMB3_CLTT_CLK), reg32); } // UART0_RTS - reg32 = read32((void *)PCH_PCR_ADDRESS(PID_GPIOCOM1, + reg32 = read32p(PCH_PCR_ADDRESS(PID_GPIOCOM1, R_PAD_CFG_DW0_PCIE_CLKREQ5_N)); if (((reg32 & B_PCH_GPIO_PAD_MODE) >> N_PCH_GPIO_PAD_MODE) != V_PCH_GPIO_PAD_MODE_NAT_3) { reg32 &= ~B_PCH_GPIO_PAD_MODE; reg32 |= (UINT32)(V_PCH_GPIO_PAD_MODE_NAT_3 << N_PCH_GPIO_PAD_MODE); - write32((void *)PCH_PCR_ADDRESS(PID_GPIOCOM1, + write32p(PCH_PCR_ADDRESS(PID_GPIOCOM1, R_PAD_CFG_DW0_PCIE_CLKREQ5_N), reg32); } @@ -115,7 +115,7 @@ reg32 &= ~B_PCH_GPIO_PAD_MODE; reg32 |= (UINT32)(V_PCH_GPIO_PAD_MODE_NAT_1 << N_PCH_GPIO_PAD_MODE); - write32((void *)PCH_PCR_ADDRESS(PID_GPIOCOM1, + write32p(PCH_PCR_ADDRESS(PID_GPIOCOM1, R_PAD_CFG_DW0_UART1_RXD), reg32); } @@ -127,31 +127,31 @@ reg32 &= ~B_PCH_GPIO_PAD_MODE; reg32 |= (UINT32)(V_PCH_GPIO_PAD_MODE_NAT_1 << N_PCH_GPIO_PAD_MODE); - write32((void *)PCH_PCR_ADDRESS(PID_GPIOCOM1, + write32p(PCH_PCR_ADDRESS(PID_GPIOCOM1, R_PAD_CFG_DW0_UART1_TXD), reg32); } // UART1_CTS - reg32 = read32((void *)PCH_PCR_ADDRESS(PID_GPIOCOM1, + reg32 = read32p(PCH_PCR_ADDRESS(PID_GPIOCOM1, R_PAD_CFG_DW0_SATA1_SDOUT)); if (((reg32 & B_PCH_GPIO_PAD_MODE) >> N_PCH_GPIO_PAD_MODE) != V_PCH_GPIO_PAD_MODE_NAT_1) { reg32 &= ~B_PCH_GPIO_PAD_MODE; reg32 |= (UINT32)(V_PCH_GPIO_PAD_MODE_NAT_1 << N_PCH_GPIO_PAD_MODE); - write32((void *)PCH_PCR_ADDRESS(PID_GPIOCOM1, + write32p(PCH_PCR_ADDRESS(PID_GPIOCOM1, R_PAD_CFG_DW0_SATA1_SDOUT), reg32); } // UART1_RTS - reg32 = read32((void *)PCH_PCR_ADDRESS(PID_GPIOCOM1, + reg32 = read32p(PCH_PCR_ADDRESS(PID_GPIOCOM1, R_PAD_CFG_DW0_SATA0_SDOUT)); if (((reg32 & B_PCH_GPIO_PAD_MODE) >> N_PCH_GPIO_PAD_MODE) != V_PCH_GPIO_PAD_MODE_NAT_1) { reg32 &= ~B_PCH_GPIO_PAD_MODE; reg32 |= (UINT32)(V_PCH_GPIO_PAD_MODE_NAT_1 << N_PCH_GPIO_PAD_MODE); - write32((void *)PCH_PCR_ADDRESS(PID_GPIOCOM1, + write32p(PCH_PCR_ADDRESS(PID_GPIOCOM1, R_PAD_CFG_DW0_SATA0_SDOUT), reg32); } diff --git a/src/soc/intel/denverton_ns/gpio_dnv.c b/src/soc/intel/denverton_ns/gpio_dnv.c index 299f950..380e619 100644 --- a/src/soc/intel/denverton_ns/gpio_dnv.c +++ b/src/soc/intel/denverton_ns/gpio_dnv.c @@ -111,7 +111,7 @@ PadNumber %= 8; Mask = ((1 << 1) | (1 << 0)) << (PadNumber * 4);
- PadOwnRegValue = read32((void *)PCH_PCR_ADDRESS( + PadOwnRegValue = read32p(PCH_PCR_ADDRESS( GpioGroupInfo[GroupIndex].Community, RegOffset));
*PadOwnVal = (GPIO_PAD_OWN)((PadOwnRegValue & Mask) >> (PadNumber * 4)); @@ -379,7 +379,7 @@ // PadCfgReg = 0x8 * PadNumber + GpioGroupInfo[GroupIndex].PadCfgOffset; - Data32 = read32((void *)PCH_PCR_ADDRESS( + Data32 = read32p(PCH_PCR_ADDRESS( GpioGroupInfo[GroupIndex].Community, PadCfgReg));
FinalValue = ((Data32 & (~Dw0RegMask)) | Dw0Reg); @@ -408,7 +408,7 @@ ~(uint32_t)Dw0RegMask, (uint32_t)Dw0Reg); }
- Data32 = read32((void *)PCH_PCR_ADDRESS( + Data32 = read32p(PCH_PCR_ADDRESS( GpioGroupInfo[GroupIndex].Community, PadCfgReg + 0x4)); FinalValue = ((Data32 & (~Dw1RegMask)) | Dw1Reg); if (Data32 != FinalValue) { diff --git a/src/soc/intel/denverton_ns/lpc.c b/src/soc/intel/denverton_ns/lpc.c index 7ebca1e..7eeb3c2 100644 --- a/src/soc/intel/denverton_ns/lpc.c +++ b/src/soc/intel/denverton_ns/lpc.c @@ -320,60 +320,60 @@ config_t *config = config_of(dev);
/* Initialize PIRQ Routings */ - write8((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIRQA_ROUT), + write8p(PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIRQA_ROUT), config->pirqa_routing); - write8((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIRQB_ROUT), + write8p(PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIRQB_ROUT), config->pirqb_routing); - write8((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIRQC_ROUT), + write8p(PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIRQC_ROUT), config->pirqc_routing); - write8((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIRQD_ROUT), + write8p(PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIRQD_ROUT), config->pirqd_routing);
- write8((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIRQE_ROUT), + write8p(PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIRQE_ROUT), config->pirqe_routing); - write8((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIRQF_ROUT), + write8p(PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIRQF_ROUT), config->pirqf_routing); - write8((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIRQG_ROUT), + write8p(PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIRQG_ROUT), config->pirqg_routing); - write8((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIRQH_ROUT), + write8p(PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIRQH_ROUT), config->pirqh_routing);
/* Initialize device's Interrupt Routings */ - write16((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR00), + write16p(PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR00), config->ir00_routing); - write16((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR01), + write16p(PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR01), config->ir01_routing); - write16((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR02), + write16p(PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR02), config->ir02_routing); - write16((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR03), + write16p(PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR03), config->ir03_routing); - write16((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR04), + write16p(PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR04), config->ir04_routing); - write16((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR05), + write16p(PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR05), config->ir05_routing); - write16((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR06), + write16p(PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR06), config->ir06_routing); - write16((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR07), + write16p(PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR07), config->ir07_routing); - write16((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR08), + write16p(PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR08), config->ir08_routing); - write16((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR09), + write16p(PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR09), config->ir09_routing); - write16((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR10), + write16p(PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR10), config->ir10_routing); - write16((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR11), + write16p(PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR11), config->ir11_routing); - write16((void *)PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR12), + write16p(PCH_PCR_ADDRESS(PID_ITSS, PCR_ITSS_PIR12), config->ir12_routing);
/* Initialize device's Interrupt Polarity Control */ - write32((void *)PCH_PCR_ADDRESS(PID_ITSS, PCH_PCR_ITSS_IPC0), + write32p(PCH_PCR_ADDRESS(PID_ITSS, PCH_PCR_ITSS_IPC0), config->ipc0); - write32((void *)PCH_PCR_ADDRESS(PID_ITSS, PCH_PCR_ITSS_IPC1), + write32p(PCH_PCR_ADDRESS(PID_ITSS, PCH_PCR_ITSS_IPC1), config->ipc1); - write32((void *)PCH_PCR_ADDRESS(PID_ITSS, PCH_PCR_ITSS_IPC2), + write32p(PCH_PCR_ADDRESS(PID_ITSS, PCH_PCR_ITSS_IPC2), config->ipc2); - write32((void *)PCH_PCR_ADDRESS(PID_ITSS, PCH_PCR_ITSS_IPC3), + write32p(PCH_PCR_ADDRESS(PID_ITSS, PCH_PCR_ITSS_IPC3), config->ipc3);
for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { diff --git a/src/soc/intel/denverton_ns/romstage.c b/src/soc/intel/denverton_ns/romstage.c index 2f3a5cc..20430b8 100644 --- a/src/soc/intel/denverton_ns/romstage.c +++ b/src/soc/intel/denverton_ns/romstage.c @@ -68,7 +68,7 @@ if (silicon_stepping() == SILICON_REV_DENVERTON_B0) { if (!(pci_read_config32(dev, GEN_PMCON_B) & GEN_PMCON_B_RTC_PWR_STS)) { - if (read32((void *)(pwrm_base + 0x124)) + if (read32p((pwrm_base + 0x124)) & ((1 << 11) | (1 << 12))) { /* Performs a global reset */ printk(BIOS_DEBUG, diff --git a/src/soc/intel/denverton_ns/sata.c b/src/soc/intel/denverton_ns/sata.c index 3fb5d75..ee4ef8f 100644 --- a/src/soc/intel/denverton_ns/sata.c +++ b/src/soc/intel/denverton_ns/sata.c @@ -39,9 +39,9 @@ printk(BIOS_DEBUG, "ABAR: %08X\n", abar);
/* Enable AHCI Mode */ - reg32 = read32((void *)(abar + 0x04)); + reg32 = read32p((abar + 0x04)); reg32 |= (1 << 31); - write32((void *)(abar + 0x04), reg32); + write32p((abar + 0x04), reg32); }
static void sata_enable(struct device *dev) { /* TODO */ } diff --git a/src/soc/intel/meteorlake/crashlog.c b/src/soc/intel/meteorlake/crashlog.c index 52d2371..b3159f5 100644 --- a/src/soc/intel/meteorlake/crashlog.c +++ b/src/soc/intel/meteorlake/crashlog.c @@ -5,6 +5,7 @@ #include <cpu/cpu.h> #include <cpu/intel/cpu_ids.h> #include <delay.h> +#include <device/mmio.h> #include <device/pci_ops.h> #include <intelblocks/crashlog.h> #include <intelblocks/pmc_ipc.h> @@ -34,7 +35,7 @@
static u64 get_disc_tab_header(void) { - return read64((void *)disc_tab_addr); + return read64p(disc_tab_addr); }
/* Get the SRAM BAR. */ @@ -362,7 +363,7 @@ break; }
- cpu_cl_disc_tab.buffers[i].data = read64((void *)(disc_tab_addr + cur_offset)); + cpu_cl_disc_tab.buffers[i].data = read64p((disc_tab_addr + cur_offset)); printk(BIOS_DEBUG, "cpu_crashlog_discovery_table buffer: 0x%x size: " "0x%x offset: 0x%x\n", i, cpu_cl_disc_tab.buffers[i].fields.size, cpu_cl_disc_tab.buffers[i].fields.offset); diff --git a/src/soc/intel/xeon_sp/spr/soc_acpi.c b/src/soc/intel/xeon_sp/spr/soc_acpi.c index 9d2df2c..0e10ab5 100644 --- a/src/soc/intel/xeon_sp/spr/soc_acpi.c +++ b/src/soc/intel/xeon_sp/spr/soc_acpi.c @@ -32,7 +32,7 @@ { /* PMC controller is hidden - hence PWRMBASE can't be accessbile using PCI cfg space */ uintptr_t pmc_bar = PCH_PWRM_BASE_ADDRESS; - return read32((void *)pmc_bar + PMC_ACPI_CNT); + return read32p(pmc_bar + PMC_ACPI_CNT); }
void soc_fill_fadt(acpi_fadt_t *fadt) diff --git a/src/soc/mediatek/common/tracker.c b/src/soc/mediatek/common/tracker.c index 3485449..c16ccf1 100644 --- a/src/soc/mediatek/common/tracker.c +++ b/src/soc/mediatek/common/tracker.c @@ -21,7 +21,7 @@ for (j = 0; j < TRACKER_NUM; j++) { tra = &tracker_data[j];
- if (!(read32((void *)(tra->base_addr)) & tra->timeout)) + if (!(read32p((tra->base_addr)) & tra->timeout)) continue;
printk(BIOS_INFO, "**Dump %s debug register start**\n", tra->str); @@ -29,7 +29,7 @@ size = 2 * tra->entry; for (i = 0; i < size; i++) { reg = tra->base_addr + tra->offset[k] + i * 4; - printk(BIOS_INFO, "%#lx:%#x,", reg, read32((void *)reg)); + printk(BIOS_INFO, "%#lx:%#x,", reg, read32p(reg));
if (i % 4 == 3 || i == size - 1) printk(BIOS_INFO, "\n"); diff --git a/src/soc/mediatek/common/tracker_v2.c b/src/soc/mediatek/common/tracker_v2.c index fecde16..5cb90fc 100644 --- a/src/soc/mediatek/common/tracker_v2.c +++ b/src/soc/mediatek/common/tracker_v2.c @@ -57,16 +57,16 @@ * peri tracker clock: 78MHz */ val = 156 * 1000 / 16 * 200; - write32((void *)(INFRA_TRACKER_BASE + BUS_DBG_TIMER_CON0), val); - write32((void *)(INFRA_TRACKER_BASE + BUS_DBG_TIMER_CON1), val); + write32p((INFRA_TRACKER_BASE + BUS_DBG_TIMER_CON0), val); + write32p((INFRA_TRACKER_BASE + BUS_DBG_TIMER_CON1), val);
val = 78 * 1000 / 16 * 200; - write32((void *)(PERI_TRACKER_BASE + BUS_DBG_TIMER_CON0), val); - write32((void *)(PERI_TRACKER_BASE + BUS_DBG_TIMER_CON1), val); + write32p((PERI_TRACKER_BASE + BUS_DBG_TIMER_CON0), val); + write32p((PERI_TRACKER_BASE + BUS_DBG_TIMER_CON1), val);
/* Enable infra/peri tracer because tracker and tracer share the same enable bit. */ - write32((void *)(BUS_TRACE_MONITOR_BASE + BUS_TRACE_CON_1), 1 << BUS_TRACE_EN); - write32((void *)(BUS_TRACE_MONITOR_BASE + BUS_TRACE_CON_2), 1 << BUS_TRACE_EN); + write32p((BUS_TRACE_MONITOR_BASE + BUS_TRACE_CON_1), 1 << BUS_TRACE_EN); + write32p((BUS_TRACE_MONITOR_BASE + BUS_TRACE_CON_2), 1 << BUS_TRACE_EN);
/* * Enable infra/peri tracker. @@ -77,6 +77,6 @@ * bit[14] - BUS_OT_WEN_CTRL */ val = BIT(0) | BIT(1) | BIT(2) | BIT(13) | BIT(14); - write32((void *)(BUS_TRACE_MONITOR_BASE + BUS_TRACE_CON_AO_1), val); - write32((void *)(BUS_TRACE_MONITOR_BASE + BUS_TRACE_CON_AO_2), val); + write32p((BUS_TRACE_MONITOR_BASE + BUS_TRACE_CON_AO_1), val); + write32p((BUS_TRACE_MONITOR_BASE + BUS_TRACE_CON_AO_2), val); } diff --git a/src/soc/mediatek/common/ufs.c b/src/soc/mediatek/common/ufs.c index 2537fa7..8cab08e 100644 --- a/src/soc/mediatek/common/ufs.c +++ b/src/soc/mediatek/common/ufs.c @@ -1,9 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */
+#include <device/mmio.h> #include <soc/ufs.h>
void ufs_disable_refclk(void) { /* disable ref clock to let UFSHCI release SPM signal */ - write32((void *)UFS_REFCLK_CTRL, 0); + write32p(UFS_REFCLK_CTRL, 0); } diff --git a/src/soc/mediatek/mt8183/ddp.c b/src/soc/mediatek/mt8183/ddp.c index 395c821..cd5e831 100644 --- a/src/soc/mediatek/mt8183/ddp.c +++ b/src/soc/mediatek/mt8183/ddp.c @@ -70,7 +70,7 @@ { disp_clock_on(); /* Turn off M4U port. */ - write32((void *)(SMI_LARB0 + SMI_LARB_NON_SEC_CON), 0); + write32p((SMI_LARB0 + SMI_LARB_NON_SEC_CON), 0); }
void mtk_ddp_mode_set(const struct edid *edid) diff --git a/src/soc/mediatek/mt8186/ddp.c b/src/soc/mediatek/mt8186/ddp.c index 5a5f544..e897cb3 100644 --- a/src/soc/mediatek/mt8186/ddp.c +++ b/src/soc/mediatek/mt8186/ddp.c @@ -6,6 +6,7 @@ */
#include <console/console.h> +#include <device/mmio.h> #include <edid.h> #include <soc/addressmap.h> #include <soc/ddp.h> @@ -138,7 +139,7 @@ disp_clock_on();
/* Turn off M4U port */ - write32((void *)(SMI_LARB0 + SMI_LARB_PORT_L0_OVL_RDMA0), 0); + write32p((SMI_LARB0 + SMI_LARB_PORT_L0_OVL_RDMA0), 0); }
void mtk_ddp_mode_set(const struct edid *edid, enum disp_path_sel path) diff --git a/src/soc/mediatek/mt8186/gic.c b/src/soc/mediatek/mt8186/gic.c index ac07764..f18b918 100644 --- a/src/soc/mediatek/mt8186/gic.c +++ b/src/soc/mediatek/mt8186/gic.c @@ -14,7 +14,7 @@ int i;
for (i = 3; i < 15; i++) { - write32((void *)((uintptr_t)MCUSYS_BASE + 0xA600 + i * 4), 0); - write32((void *)((uintptr_t)MCUSYS_BASE + 0xA650 + i * 4), 0xFFFFFFFF); + write32p(((uintptr_t)MCUSYS_BASE + 0xA600 + i * 4), 0); + write32p(((uintptr_t)MCUSYS_BASE + 0xA650 + i * 4), 0xFFFFFFFF); } } diff --git a/src/soc/mediatek/mt8186/spm.c b/src/soc/mediatek/mt8186/spm.c index 00e2c27..04680b1 100644 --- a/src/soc/mediatek/mt8186/spm.c +++ b/src/soc/mediatek/mt8186/spm.c @@ -6,6 +6,7 @@ */
#include <assert.h> +#include <device/mmio.h> #include <soc/mcu_common.h> #include <soc/spm.h>
@@ -425,10 +426,10 @@ write32(&mtk_spm->spm_resource_ack_con3, SPM_RESOURCE_ACK_CON3_DEF);
/* Enable Side-Band */ - write32((void *)AP_PLL_CON3, APMIX_CON3_DEF); - write32((void *)AP_PLL_CON4, APMIX_CON4_DEF); - write32((void *)CLK_SCP_CFG_0, SCP_CFG0_DEF); - write32((void *)CLK_SCP_CFG_1, SCP_CFG1_DEF); + write32p(AP_PLL_CON3, APMIX_CON3_DEF); + write32p(AP_PLL_CON4, APMIX_CON4_DEF); + write32p(CLK_SCP_CFG_0, SCP_CFG0_DEF); + write32p(CLK_SCP_CFG_1, SCP_CFG1_DEF);
/* Init VCORE DVFS Status */ SET32_BITFIELDS(&mtk_spm->spm_dvfs_misc, diff --git a/src/soc/mediatek/mt8192/ddp.c b/src/soc/mediatek/mt8192/ddp.c index f03a902..a8875e85 100644 --- a/src/soc/mediatek/mt8192/ddp.c +++ b/src/soc/mediatek/mt8192/ddp.c @@ -171,7 +171,7 @@ { disp_clock_on(); /* Turn off M4U port. */ - write32((void *)(SMI_LARB0 + SMI_LARB_PORT_L0_OVL_RDMA0), 0); + write32p((SMI_LARB0 + SMI_LARB_PORT_L0_OVL_RDMA0), 0); }
void mtk_ddp_mode_set(const struct edid *edid) diff --git a/src/soc/mediatek/mt8195/apusys_devapc.c b/src/soc/mediatek/mt8195/apusys_devapc.c index 0c8d10f..dc635b4 100644 --- a/src/soc/mediatek/mt8195/apusys_devapc.c +++ b/src/soc/mediatek/mt8195/apusys_devapc.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only OR MIT */
#include <console/console.h> +#include <device/mmio.h> #include <soc/apusys_devapc.h> #include <soc/devapc.h>
@@ -181,7 +182,7 @@ for (d = 0U; d < APUSYS_NOC_DAPC_AO_DOM_NUM; d++) { for (i = 0U; i < reg_num; i++) printk(BIOS_DEBUG, "[NOCDAPC] D%ld_APC_%ld: %#x\n", d, i, - read32((void *)(APUSYS_NOC_DAPC_AO_BASE + d * 0x40 + i * 4))); + read32p((APUSYS_NOC_DAPC_AO_BASE + d * 0x40 + i * 4))); } printk(BIOS_DEBUG, "[NOCDAPC] APC_CON: %#x\n", read32(APUSYS_NOC_DAPC_CON)); } @@ -222,7 +223,7 @@ for (d = 0U; d < APUSYS_APC_SYS0_AO_DOM_NUM; d++) { for (i = 0U; i < reg_num; i++) printk(BIOS_DEBUG, "[APUAPC] D%ld_APC_%ld: %#x\n", d, i, - read32((void *)(APUSYS_APC_AO_BASE + d * 0x40 + i * 4))); + read32p((APUSYS_APC_AO_BASE + d * 0x40 + i * 4))); } printk(BIOS_DEBUG, "[APUAPC] APC_CON: %#x\n", read32(APUSYS_APC_CON)); } diff --git a/src/soc/mediatek/mt8195/ddp.c b/src/soc/mediatek/mt8195/ddp.c index 2bd95a2..0543ef4 100644 --- a/src/soc/mediatek/mt8195/ddp.c +++ b/src/soc/mediatek/mt8195/ddp.c @@ -147,7 +147,7 @@ disp_clock_on();
/* Turn off M4U port. */ - write32((void *)(SMI_LARB0 + SMI_LARB_PORT_L0_OVL_RDMA0), 0); + write32p((SMI_LARB0 + SMI_LARB_PORT_L0_OVL_RDMA0), 0); }
void mtk_ddp_mode_set(const struct edid *edid, enum disp_path_sel path) diff --git a/src/soc/mediatek/mt8195/hdmi.c b/src/soc/mediatek/mt8195/hdmi.c index 9b343f4..65adee4 100644 --- a/src/soc/mediatek/mt8195/hdmi.c +++ b/src/soc/mediatek/mt8195/hdmi.c @@ -11,15 +11,15 @@ setbits32((void *)HDMI_PROTECT_REG, BIT(0) | BIT(1));
/* HDMI-RX powerdown */ - write32((void *)HDMI_RX_PDN_0_REG, HDMI_RX_PDN_0_VAL); - write32((void *)HDMI_RX_PDN_1_REG, HDMI_RX_PDN_1_VAL); - write32((void *)HDMI_RX_PDN_2_REG, HDMI_RX_PDN_2_VAL); - write32((void *)HDMI_RX_PDN_3_REG, HDMI_RX_PDN_3_VAL); - write32((void *)HDMI_RX_PDN_4_REG, HDMI_RX_PDN_4_VAL); - write32((void *)HDMI_RX_PDN_5_REG, HDMI_RX_PDN_5_VAL); - write32((void *)HDMI_RX_PDN_6_REG, HDMI_RX_PDN_6_VAL); - write32((void *)HDMI_RX_PDN_7_REG, HDMI_RX_PDN_7_VAL); + write32p(HDMI_RX_PDN_0_REG, HDMI_RX_PDN_0_VAL); + write32p(HDMI_RX_PDN_1_REG, HDMI_RX_PDN_1_VAL); + write32p(HDMI_RX_PDN_2_REG, HDMI_RX_PDN_2_VAL); + write32p(HDMI_RX_PDN_3_REG, HDMI_RX_PDN_3_VAL); + write32p(HDMI_RX_PDN_4_REG, HDMI_RX_PDN_4_VAL); + write32p(HDMI_RX_PDN_5_REG, HDMI_RX_PDN_5_VAL); + write32p(HDMI_RX_PDN_6_REG, HDMI_RX_PDN_6_VAL); + write32p(HDMI_RX_PDN_7_REG, HDMI_RX_PDN_7_VAL);
/* HDMI-TX powerdown */ - write32((void *)HDMI_TX_PDN_REG, HDMI_TX_PDN_VAL); + write32p(HDMI_TX_PDN_REG, HDMI_TX_PDN_VAL); } diff --git a/src/soc/mediatek/mt8195/usb.c b/src/soc/mediatek/mt8195/usb.c index 6902bd8..d58071d 100644 --- a/src/soc/mediatek/mt8195/usb.c +++ b/src/soc/mediatek/mt8195/usb.c @@ -18,7 +18,7 @@ SET32_BITFIELDS(&phy->u3phyd.phyd_reserved, AUTO_LOAD_DIS, 1);
- phy_set_val = read32((void *)USB_PHY_SETTING_REG); + phy_set_val = read32p(USB_PHY_SETTING_REG);
/* TX imp */ write_val = (phy_set_val & TX_IMP_MASK) >> TX_IMP_SHIFT; diff --git a/src/soc/nvidia/tegra/apbmisc.c b/src/soc/nvidia/tegra/apbmisc.c index bc026c1..8bc443b 100644 --- a/src/soc/nvidia/tegra/apbmisc.c +++ b/src/soc/nvidia/tegra/apbmisc.c @@ -22,7 +22,7 @@ uintptr_t gp_hidrev= (uintptr_t)TEGRA_APB_MISC_BASE + MISC_GP_HIDREV; uint32_t reg;
- reg = read32((void *)(gp_hidrev)); + reg = read32p((gp_hidrev));
id->hid_fam = (reg >> 0) & 0x0f; id->chip_id = (reg >> 8) & 0xff; diff --git a/src/soc/nvidia/tegra124/monotonic_timer.c b/src/soc/nvidia/tegra124/monotonic_timer.c index 52d5335..de90c0b 100644 --- a/src/soc/nvidia/tegra124/monotonic_timer.c +++ b/src/soc/nvidia/tegra124/monotonic_timer.c @@ -6,5 +6,5 @@
void timer_monotonic_get(struct mono_time *mt) { - mono_time_set_usecs(mt, read32((void *)TEGRA_TMRUS_BASE)); + mono_time_set_usecs(mt, read32p(TEGRA_TMRUS_BASE)); } diff --git a/src/soc/nvidia/tegra210/bootblock.c b/src/soc/nvidia/tegra210/bootblock.c index e8c4324..d1f37b0 100644 --- a/src/soc/nvidia/tegra210/bootblock.c +++ b/src/soc/nvidia/tegra210/bootblock.c @@ -33,9 +33,9 @@ // pick up the ODMDATA word at BCT offset 0x6A8. I could use a BCT // struct header from cbootimage, but it seems like overkill for this.
- bct_offset = read32((void *)(TEGRA_SRAM_BASE + BCT_OFFSET_IN_BIT)); + bct_offset = read32p((TEGRA_SRAM_BASE + BCT_OFFSET_IN_BIT)); if (bct_offset > TEGRA_SRAM_BASE && bct_offset < TEGRA_SRAM_MAX) { - odmdata = read32((void *)(bct_offset + ODMDATA_OFFSET_IN_BCT)); + odmdata = read32p((bct_offset + ODMDATA_OFFSET_IN_BCT)); write32(&pmc->odmdata, odmdata); } } @@ -130,10 +130,10 @@ val = wa_op->val; break; case OP_OR: - val = read32((void *)wa_op->reg) | wa_op->val; + val = read32p(wa_op->reg) | wa_op->val; break; case OP_AND: - val = read32((void *)wa_op->reg) & wa_op->val; + val = read32p(wa_op->reg) & wa_op->val; break; case OP_UDELAY: udelay(wa_op->val); @@ -141,7 +141,7 @@ default: continue; } - write32((void *)wa_op->reg, val); + write32p(wa_op->reg, val); } }
diff --git a/src/soc/nvidia/tegra210/clock.c b/src/soc/nvidia/tegra210/clock.c index 4433d7e..4ff859c 100644 --- a/src/soc/nvidia/tegra210/clock.c +++ b/src/soc/nvidia/tegra210/clock.c @@ -576,7 +576,7 @@ CLK_M_DIVISOR_BY_2);
/* TIMERUS needs to be adjusted for new 19.2MHz CLK_M rate */ - write32((void *)TEGRA_TMRUS_BASE + TIMERUS_USEC_CFG, + write32p(TEGRA_TMRUS_BASE + TIMERUS_USEC_CFG, TIMERUS_USEC_CFG_19P2_CLK_M);
init_pllc(osc); diff --git a/src/soc/nvidia/tegra210/i2c6.c b/src/soc/nvidia/tegra210/i2c6.c index 338ac8b..cbadeac 100644 --- a/src/soc/nvidia/tegra210/i2c6.c +++ b/src/soc/nvidia/tegra210/i2c6.c @@ -52,9 +52,9 @@ clock_enable_y(CLK_Y_DPAUX1 | CLK_Y_SOR_SAFE);
/* Now we can write the I2C6 mux in DPAUX */ - write32((void *)DPAUX_HYBRID_PADCTL, I2C6_PADCTL); + write32p(DPAUX_HYBRID_PADCTL, I2C6_PADCTL); /* Finally, power up the pads */ - write32((void *)DPAUX_HYBRID_SPARE, 0); + write32p(DPAUX_HYBRID_SPARE, 0);
/* * Delay before turning off Host1X/DPAUX clocks. diff --git a/src/soc/nvidia/tegra210/monotonic_timer.c b/src/soc/nvidia/tegra210/monotonic_timer.c index 52d5335..de90c0b 100644 --- a/src/soc/nvidia/tegra210/monotonic_timer.c +++ b/src/soc/nvidia/tegra210/monotonic_timer.c @@ -6,5 +6,5 @@
void timer_monotonic_get(struct mono_time *mt) { - mono_time_set_usecs(mt, read32((void *)TEGRA_TMRUS_BASE)); + mono_time_set_usecs(mt, read32p(TEGRA_TMRUS_BASE)); } diff --git a/src/soc/nvidia/tegra210/ramstage.c b/src/soc/nvidia/tegra210/ramstage.c index 45b221b..e313ef0 100644 --- a/src/soc/nvidia/tegra210/ramstage.c +++ b/src/soc/nvidia/tegra210/ramstage.c @@ -27,13 +27,13 @@ #define WRAP_TO_INCR_SLAVE1 (0x1 << 28) #define WRAP_TO_INCR_SLAVE2 (0x1 << 29)
- reg = read32((void *)TEGRA_MSELECT_CONFIG); + reg = read32p(TEGRA_MSELECT_CONFIG); /* Disable error mechanism */ reg &= ~(ERR_RESP_EN_SLAVE1 | ERR_RESP_EN_SLAVE2); /* Enable WRAP type conversion */ reg |= (WRAP_TO_INCR_SLAVE0 | WRAP_TO_INCR_SLAVE1 | WRAP_TO_INCR_SLAVE2); - write32((void *)TEGRA_MSELECT_CONFIG, reg); + write32p(TEGRA_MSELECT_CONFIG, reg); }
/* Tegra-specific entry point, called from assembly in stage_entry.S */ diff --git a/src/soc/qualcomm/common/qupv3_config.c b/src/soc/qualcomm/common/qupv3_config.c index 636f9b2..c4860f4 100644 --- a/src/soc/qualcomm/common/qupv3_config.c +++ b/src/soc/qualcomm/common/qupv3_config.c @@ -4,6 +4,7 @@ #include <string.h> #include <soc/qupv3_config_common.h> #include <console/console.h> +#include <device/mmio.h> #include <soc/qup_se_handlers_common.h> #include <soc/qcom_qup_se.h> #include <soc/addressmap.h> @@ -215,7 +216,7 @@ for (i = 0; i < gsi_hdr->iep_size_in_items; i++) { /* Check if offset does not exceed GSI address space size */ if (fwIep[i].offset < GSI_REG_BASE_SIZE) - write32((void *)®s->gsi_cfg + fwIep[i].offset, + write32p(®s->gsi_cfg + fwIep[i].offset, fwIep[i].value); }
diff --git a/src/soc/qualcomm/sc7280/socinfo.c b/src/soc/qualcomm/sc7280/socinfo.c index 8046237..c544464 100644 --- a/src/soc/qualcomm/sc7280/socinfo.c +++ b/src/soc/qualcomm/sc7280/socinfo.c @@ -40,7 +40,7 @@
static uint16_t read_jtagid(void) { - return (read32((void *)(TLMM_TILE_BASE + JTAG_OFFSET)) & DEVICE_ID); + return (read32p((TLMM_TILE_BASE + JTAG_OFFSET)) & DEVICE_ID); }
static int match_jtagid(uint16_t jtagid) diff --git a/src/soc/samsung/exynos5250/cpu.c b/src/soc/samsung/exynos5250/cpu.c index 06c9423..c246853 100644 --- a/src/soc/samsung/exynos5250/cpu.c +++ b/src/soc/samsung/exynos5250/cpu.c @@ -17,7 +17,7 @@
static void set_cpu_id(void) { - cpu_id = read32((void *)EXYNOS5_PRO_ID); + cpu_id = read32p(EXYNOS5_PRO_ID); cpu_id = (0xC000 | ((cpu_id & 0x00FFF000) >> 12));
/* diff --git a/src/soc/samsung/exynos5420/cpu.c b/src/soc/samsung/exynos5420/cpu.c index 7869ab8..bd8e83a 100644 --- a/src/soc/samsung/exynos5420/cpu.c +++ b/src/soc/samsung/exynos5420/cpu.c @@ -18,7 +18,7 @@
static void set_cpu_id(void) { - u32 pro_id = (read32((void *)EXYNOS5_PRO_ID) & 0x00FFF000) >> 12; + u32 pro_id = (read32p(EXYNOS5_PRO_ID) & 0x00FFF000) >> 12;
switch (pro_id) { case 0x200: diff --git a/src/soc/samsung/exynos5420/dp_lowlevel.c b/src/soc/samsung/exynos5420/dp_lowlevel.c index 2d33873..b8e129f 100644 --- a/src/soc/samsung/exynos5420/dp_lowlevel.c +++ b/src/soc/samsung/exynos5420/dp_lowlevel.c @@ -33,8 +33,8 @@
#define lread32(a) fradl((void *)(a)) #else -#define lwrite32(a,b) write32((void *)(b), (unsigned long)(a)) -#define lread32(a) read32((void *)(a)) +#define lwrite32(a,b) write32p((b), (unsigned long)(a)) +#define lread32(a) read32p((a)) #endif
static void exynos_dp_enable_video_input(u32 enable) @@ -657,7 +657,7 @@
for (cur_data_idx = 0; cur_data_idx < cur_data_count; cur_data_idx++) { - reg = lread32((void *)((u32)&dp_regs->buf_data0 + + reg = lread32p(((u32)&dp_regs->buf_data0 + 4 * cur_data_idx)); data[start_offset + cur_data_idx] = (unsigned char)reg; } @@ -801,7 +801,7 @@ }
for (cur_data_idx = 0; cur_data_idx < 16; cur_data_idx++) { - reg = lread32((void *)((u32)&dp_regs->buf_data0 + reg = lread32p(((u32)&dp_regs->buf_data0 + 4 * cur_data_idx)); edid[i + cur_data_idx] = (unsigned char)reg; } diff --git a/src/soc/samsung/exynos5420/fimd.c b/src/soc/samsung/exynos5420/fimd.c index bf236d3..4c4f605 100644 --- a/src/soc/samsung/exynos5420/fimd.c +++ b/src/soc/samsung/exynos5420/fimd.c @@ -25,8 +25,8 @@ #define lreadl(a) fradl((void *)(a))
#else -#define lwritel(a,b) write32((void *)(b), (unsigned long)(a)) -#define lreadl(a) read32((void *)(a)) +#define lwritel(a,b) write32p((b), (unsigned long)(a)) +#define lreadl(a) read32p((a)) #endif
/* not sure where we want this so ... */ diff --git a/src/soc/samsung/exynos5420/smp.c b/src/soc/samsung/exynos5420/smp.c index 13e9489..f3d9e15 100644 --- a/src/soc/samsung/exynos5420/smp.c +++ b/src/soc/samsung/exynos5420/smp.c @@ -262,7 +262,7 @@ * when we want to use SMP inside firmware. */
/* Clear boot reg (hotplug address) in CPU states */ - write32((void *)&exynos_cpu_states->hotplug_address, 0); + write32p(&exynos_cpu_states->hotplug_address, 0);
/* set low_power flag and address */ write32(VECTOR_LOW_POWER_ADDRESS, (intptr_t)low_power_start); diff --git a/src/soc/sifive/fu540/clint.c b/src/soc/sifive/fu540/clint.c index 08124d3..7ab5c59 100644 --- a/src/soc/sifive/fu540/clint.c +++ b/src/soc/sifive/fu540/clint.c @@ -14,5 +14,5 @@
void set_msip(int hartid, int val) { - write32((void *)(FU540_CLINT + 4 * (uintptr_t)hartid), !!val); + write32p((FU540_CLINT + 4 * (uintptr_t)hartid), !!val); }
-
Elyes Haouas (Code Review)