Change in coreboot[master]: soc/tigerlake: Update FSP UPDs to turn on USB4/TBT

[Brandon Breitenstein (Code Review)]

Brandon Breitenstein has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38737 )

Change subject: soc/tigerlake: Update FSP UPDs to turn on USB4/TBT
......................................................................

soc/tigerlake: Update FSP UPDs to turn on USB4/TBT

FSP needs to know to allow the root ports for USB4/TBT to be enabled
This patch may need additional checks for each board as it might not
be the right thing to turn them all on for every tigerlake board.

BUG=b:141609883
BRANCH=NONE
TEST=Built image and verified that the root ports were visible with lspci

Change-Id: I3f020e20fa8e9fd1ac69d883f4dc1fcbb330a3bf
Signed-off-by: Brandon Breitenstein 
---
M src/soc/intel/tigerlake/fsp_params_tgl.c
M src/soc/intel/tigerlake/romstage/fsp_params_tgl.c
2 files changed, 11 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/38737/1

diff --git a/src/soc/intel/tigerlake/fsp_params_tgl.c b/src/soc/intel/tigerlake/fsp_params_tgl.c
index 305748e..22c1b2a 100644
--- a/src/soc/intel/tigerlake/fsp_params_tgl.c
+++ b/src/soc/intel/tigerlake/fsp_params_tgl.c
@@ -135,6 +135,10 @@
    		sizeof(params->SataPortsDevSlp));
    }

+	/* USB4/TBT */
+	for (i = 0; i < 4; i++)
+		params->ITbtPcieRootPortEn[i] = 1;
+
    mainboard_silicon_init_params(params);
 }

diff --git a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c
index fc3155f..0d11306 100644
--- a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c
+++ b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c
@@ -129,6 +129,13 @@
    config = config_of_soc();

soc_memory_init_params(m_cfg, config);
+
+	/* USB4/TBT */
+	m_cfg->TcssItbtPcie0En = 1;
+	m_cfg->TcssItbtPcie1En = 1;
+	m_cfg->TcssItbtPcie2En = 1;
+	m_cfg->TcssItbtPcie3En = 1;
+
    mainboard_memory_init_params(mupd);
 }

[Paul Menzel (Code Review)]

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38737 )

Change subject: soc/tigerlake: Update FSP UPDs to turn on USB4/TBT
......................................................................

Patch Set 1: Code-Review+1

(2 comments)

https://review.coreboot.org/c/coreboot/+/38737/1//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/38737/1//COMMIT_MSG@7 
PS1, Line 7: soc/tigerlake: Update FSP UPDs to turn on USB4/TBT
soc/intel/tigerlake

https://review.coreboot.org/c/coreboot/+/38737/1//COMMIT_MSG@11 
PS1, Line 11: tigerlake
Tiger Lake

[Paul Menzel (Code Review)]

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38737 )

Change subject: soc/tigerlake: Update FSP UPDs to turn on USB4/TBT
......................................................................

Patch Set 1:

(1 comment)

https://review.coreboot.org/c/coreboot/+/38737/1/src/soc/intel/tigerlake/rom... 
File src/soc/intel/tigerlake/romstage/fsp_params_tgl.c:

https://review.coreboot.org/c/coreboot/+/38737/1/src/soc/intel/tigerlake/rom... 
PS1, Line 137: 	m_cfg->TcssItbtPcie3En = 1;
Why does the information need to be in two places?

[Aaron Durbin (Code Review)]

Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38737 )

Change subject: soc/tigerlake: Update FSP UPDs to turn on USB4/TBT
......................................................................

Patch Set 1:

(3 comments)

https://review.coreboot.org/c/coreboot/+/38737/1/src/soc/intel/tigerlake/fsp... 
File src/soc/intel/tigerlake/fsp_params_tgl.c:

https://review.coreboot.org/c/coreboot/+/38737/1/src/soc/intel/tigerlake/fsp... 
PS1, Line 139: 4
ARRAY_SIZE()

https://review.coreboot.org/c/coreboot/+/38737/1/src/soc/intel/tigerlake/fsp... 
PS1, Line 140: 		params->ITbtPcieRootPortEn[i] = 1;
This should be a devicetree config option that we can associate with the device itself. We likely could utilize the enable field of the device in question.

https://review.coreboot.org/c/coreboot/+/38737/1/src/soc/intel/tigerlake/rom... 
File src/soc/intel/tigerlake/romstage/fsp_params_tgl.c:

https://review.coreboot.org/c/coreboot/+/38737/1/src/soc/intel/tigerlake/rom... 
PS1, Line 134: 	m_cfg->TcssItbtPcie0En = 1;
Same comment as my other one relating to driving these values from devicetree.

[Brandon Breitenstein (Code Review)]

Hello build bot (Jenkins), Paul Menzel, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/38737

to look at the new patch set (#2).

Change subject: soc/tigerlake: Update FSP UPDs to turn on USB4/TBT
......................................................................

soc/tigerlake: Update FSP UPDs to turn on USB4/TBT

FSP needs to know to allow the root ports for USB4/TBT to be enabled
This patch may need additional checks for each board as it might not
be the right thing to turn them all on for every tigerlake board.

BUG=b:141609883
BRANCH=NONE
TEST=Built image and verified that the root ports were visible with lspci

Change-Id: I3f020e20fa8e9fd1ac69d883f4dc1fcbb330a3bf
Signed-off-by: Brandon Breitenstein 
---
M src/soc/intel/tigerlake/chip.h
M src/soc/intel/tigerlake/fsp_params_tgl.c
M src/soc/intel/tigerlake/romstage/fsp_params_tgl.c
3 files changed, 22 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/38737/2

[Brandon Breitenstein (Code Review)]

Brandon Breitenstein has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38737 )

Change subject: soc/tigerlake: Update FSP UPDs to turn on USB4/TBT
......................................................................

Patch Set 2:

(4 comments)

https://review.coreboot.org/c/coreboot/+/38737/1/src/soc/intel/tigerlake/fsp... 
File src/soc/intel/tigerlake/fsp_params_tgl.c:

https://review.coreboot.org/c/coreboot/+/38737/1/src/soc/intel/tigerlake/fsp... 
PS1, Line 139: 4
> ARRAY_SIZE()

Done

https://review.coreboot.org/c/coreboot/+/38737/1/src/soc/intel/tigerlake/fsp... 
PS1, Line 140: 		params->ITbtPcieRootPortEn[i] = 1;
> This should be a devicetree config option that we can associate with the device itself. […]

Done

https://review.coreboot.org/c/coreboot/+/38737/1/src/soc/intel/tigerlake/rom... 
File src/soc/intel/tigerlake/romstage/fsp_params_tgl.c:

https://review.coreboot.org/c/coreboot/+/38737/1/src/soc/intel/tigerlake/rom... 
PS1, Line 134: 	m_cfg->TcssItbtPcie0En = 1;
> Same comment as my other one relating to driving these values from devicetree.

Done

https://review.coreboot.org/c/coreboot/+/38737/1/src/soc/intel/tigerlake/rom... 
PS1, Line 137: 	m_cfg->TcssItbtPcie3En = 1;
> Why does the information need to be in two places?

This is for Tcss Config and the Soc one is for root port config

[Tim Wawrzynczak (Code Review)]

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38737 )

Change subject: soc/tigerlake: Update FSP UPDs to turn on USB4/TBT
......................................................................

Patch Set 2:

(1 comment)

https://review.coreboot.org/c/coreboot/+/38737/2/src/soc/intel/tigerlake/rom... 
File src/soc/intel/tigerlake/romstage/fsp_params_tgl.c:

https://review.coreboot.org/c/coreboot/+/38737/2/src/soc/intel/tigerlake/rom... 
PS2, Line 143: 
This extra line is unnecesssary.

[Wonkyu Kim (Code Review)]

Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38737 )

Change subject: soc/tigerlake: Update FSP UPDs to turn on USB4/TBT
......................................................................

Patch Set 2:

(2 comments)

https://review.coreboot.org/c/coreboot/+/38737/2/src/soc/intel/tigerlake/fsp... 
File src/soc/intel/tigerlake/fsp_params_tgl.c:

https://review.coreboot.org/c/coreboot/+/38737/2/src/soc/intel/tigerlake/fsp... 
PS2, Line 167: ITbtPcieRootPortEn
ITbtPcieRootPortEn[i]

https://review.coreboot.org/c/coreboot/+/38737/2/src/soc/intel/tigerlake/fsp... 
PS2, Line 169: params->ItbtPcieRootPortEn
ITbtPcieRootPortEn[i]

[Brandon Breitenstein (Code Review)]

Hello build bot (Jenkins), Furquan Shaikh, Caveh Jalali, Paul Menzel, Nick Vaccaro, Tim Wawrzynczak, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/38737

to look at the new patch set (#3).

Change subject: soc/tigerlake: Update FSP UPDs to turn on USB4/TBT
......................................................................

soc/tigerlake: Update FSP UPDs to turn on USB4/TBT

FSP needs to know to allow the root ports for USB4/TBT to be enabled
This patch may need additional checks for each board as it might not
be the right thing to turn them all on for every tigerlake board.

BUG=b:141609883
BRANCH=NONE
TEST=Built image and verified that the root ports were visible with lspci

Change-Id: I3f020e20fa8e9fd1ac69d883f4dc1fcbb330a3bf
Signed-off-by: Brandon Breitenstein 
---
M src/soc/intel/tigerlake/chip.h
M src/soc/intel/tigerlake/fsp_params_tgl.c
M src/soc/intel/tigerlake/romstage/fsp_params_tgl.c
3 files changed, 21 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/38737/3

[Brandon Breitenstein (Code Review)]

Brandon Breitenstein has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38737 )

Change subject: soc/tigerlake: Update FSP UPDs to turn on USB4/TBT
......................................................................

Patch Set 3:

(3 comments)

https://review.coreboot.org/c/coreboot/+/38737/2/src/soc/intel/tigerlake/fsp... 
File src/soc/intel/tigerlake/fsp_params_tgl.c:

https://review.coreboot.org/c/coreboot/+/38737/2/src/soc/intel/tigerlake/fsp... 
PS2, Line 167: ITbtPcieRootPortEn
> ITbtPcieRootPortEn[i]

Done

https://review.coreboot.org/c/coreboot/+/38737/2/src/soc/intel/tigerlake/fsp... 
PS2, Line 169: params->ItbtPcieRootPortEn
> ITbtPcieRootPortEn[i]

Done

https://review.coreboot.org/c/coreboot/+/38737/2/src/soc/intel/tigerlake/rom... 
File src/soc/intel/tigerlake/romstage/fsp_params_tgl.c:

https://review.coreboot.org/c/coreboot/+/38737/2/src/soc/intel/tigerlake/rom... 
PS2, Line 143:
> This extra line is unnecesssary.

Done

[Caveh Jalali (Code Review)]

Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38737 )

Change subject: soc/tigerlake: Update FSP UPDs to turn on USB4/TBT
......................................................................

Patch Set 3:

(1 comment)

https://review.coreboot.org/c/coreboot/+/38737/3/src/soc/intel/tigerlake/chi... 
File src/soc/intel/tigerlake/chip.h:

https://review.coreboot.org/c/coreboot/+/38737/3/src/soc/intel/tigerlake/chi... 
PS3, Line 235: USB4/TBT
should these be structured as an array like ITbtPcieRootPortEn?

[Brandon Breitenstein (Code Review)]

Brandon Breitenstein has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38737 )

Change subject: soc/tigerlake: Update FSP UPDs to turn on USB4/TBT
......................................................................

Patch Set 3:

(1 comment)

https://review.coreboot.org/c/coreboot/+/38737/3/src/soc/intel/tigerlake/chi... 
File src/soc/intel/tigerlake/chip.h:

https://review.coreboot.org/c/coreboot/+/38737/3/src/soc/intel/tigerlake/chi... 
PS3, Line 235: USB4/TBT
> should these be structured as an array like ITbtPcieRootPortEn?

This is a different config than ITbtPcieRootPortEn...that one is in Fsps the one that is being changed my this config is in Fspm and is for the bridge not the root port if my understanding of the to configs is correct

[Brandon Breitenstein (Code Review)]

Hello build bot (Jenkins), Furquan Shaikh, Caveh Jalali, Paul Menzel, Nick Vaccaro, Tim Wawrzynczak, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/38737

to look at the new patch set (#4).

Change subject: soc/tigerlake: Update FSP UPDs to turn on USB4/TBT
......................................................................

soc/tigerlake: Update FSP UPDs to turn on USB4/TBT

FSP needs to know to allow the root ports for USB4/TBT to be enabled
This patch may need additional checks for each board as it might not
be the right thing to turn them all on for every tigerlake board.

BUG=b:141609883
BRANCH=NONE
TEST=Built image and verified that the root ports were visible with lspci

Change-Id: I3f020e20fa8e9fd1ac69d883f4dc1fcbb330a3bf
Signed-off-by: Brandon Breitenstein 
---
M src/soc/intel/tigerlake/chip.h
M src/soc/intel/tigerlake/fsp_params_tgl.c
M src/soc/intel/tigerlake/romstage/fsp_params_tgl.c
3 files changed, 21 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/38737/4

[Wonkyu Kim (Code Review)]

Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38737 )

Change subject: soc/tigerlake: Update FSP UPDs to turn on USB4/TBT
......................................................................

Patch Set 4:

(1 comment)

https://review.coreboot.org/c/coreboot/+/38737/4/src/soc/intel/tigerlake/rom... 
File src/soc/intel/tigerlake/romstage/fsp_params_tgl.c:

https://review.coreboot.org/c/coreboot/+/38737/4/src/soc/intel/tigerlake/rom... 
PS4, Line 125: 	m_cfg->TcssItbtPcie0En = config->TcssItbtPcie0En;
             : 	m_cfg->TcssItbtPcie1En = config->TcssItbtPcie1En;
             : 	m_cfg->TcssItbtPcie2En = config->TcssItbtPcie2En;
             : 	m_cfg->TcssItbtPcie3En = config->TcssItbtPcie3En;
             : 
Can we also use same condition check for device enabled?
dev = pcidev_on_root(SA_DEV_SLOT_TBT, i);

[Brandon Breitenstein (Code Review)]

Brandon Breitenstein has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38737 )

Change subject: soc/tigerlake: Update FSP UPDs to turn on USB4/TBT
......................................................................

Patch Set 4:

(1 comment)

https://review.coreboot.org/c/coreboot/+/38737/4/src/soc/intel/tigerlake/rom... 
File src/soc/intel/tigerlake/romstage/fsp_params_tgl.c:

https://review.coreboot.org/c/coreboot/+/38737/4/src/soc/intel/tigerlake/rom... 
PS4, Line 125: 	m_cfg->TcssItbtPcie0En = config->TcssItbtPcie0En;
             : 	m_cfg->TcssItbtPcie1En = config->TcssItbtPcie1En;
             : 	m_cfg->TcssItbtPcie2En = config->TcssItbtPcie2En;
             : 	m_cfg->TcssItbtPcie3En = config->TcssItbtPcie3En;
             :
> Can we also use same condition check for device enabled? […]

we can but I was under the impression that this was a different setting and a loop really isn't useful here since the cfg is not in an array to start

[Brandon Breitenstein (Code Review)]

Hello build bot (Jenkins), Furquan Shaikh, Caveh Jalali, Paul Menzel, Nick Vaccaro, Tim Wawrzynczak, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/38737

to look at the new patch set (#5).

Change subject: soc/tigerlake: Update FSP UPDs to turn on USB4/TBT
......................................................................

soc/tigerlake: Update FSP UPDs to turn on USB4/TBT

FSP needs to know to allow the root ports for USB4/TBT to be enabled
This patch may need additional checks for each board as it might not
be the right thing to turn them all on for every tigerlake board.

BUG=b:141609883
BRANCH=NONE
TEST=Built image and verified that the root ports were visible with lspci

Change-Id: I3f020e20fa8e9fd1ac69d883f4dc1fcbb330a3bf
Signed-off-by: Brandon Breitenstein 
---
M src/soc/intel/tigerlake/fsp_params_tgl.c
M src/soc/intel/tigerlake/romstage/fsp_params_tgl.c
2 files changed, 32 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/38737/5

Change in coreboot[master]: soc/intel/tigerlake: Update FSP UPDs to turn on USB4/TBT

[Brandon Breitenstein (Code Review)]

Hello build bot (Jenkins), Furquan Shaikh, Caveh Jalali, Paul Menzel, Nick Vaccaro, Tim Wawrzynczak, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/38737

to look at the new patch set (#6).

Change subject: soc/intel/tigerlake: Update FSP UPDs to turn on USB4/TBT
......................................................................

soc/intel/tigerlake: Update FSP UPDs to turn on USB4/TBT

FSP needs to know to allow the root ports for USB4/TBT to be enabled
This patch may need additional checks for each board as it might not
be the right thing to turn them all on for every Tiger Lake board.

BUG=b:141609883
BRANCH=NONE
TEST=Built image and verified that the root ports were visible with lspci

Change-Id: I3f020e20fa8e9fd1ac69d883f4dc1fcbb330a3bf
Signed-off-by: Brandon Breitenstein 
---
M src/soc/intel/tigerlake/fsp_params_tgl.c
M src/soc/intel/tigerlake/romstage/fsp_params_tgl.c
2 files changed, 32 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/38737/6

Change in coreboot[master]: soc/intel/tigerlake: Update FSP UPDs to turn on USB4/TBT

[Brandon Breitenstein (Code Review)]

Brandon Breitenstein has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38737 )

Change subject: soc/intel/tigerlake: Update FSP UPDs to turn on USB4/TBT
......................................................................

Patch Set 5:

(4 comments)

https://review.coreboot.org/c/coreboot/+/38737/1//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/38737/1//COMMIT_MSG@7 
PS1, Line 7: soc/tigerlake: Update FSP UPDs to turn on USB4/TBT
> soc/intel/tigerlake

Done

https://review.coreboot.org/c/coreboot/+/38737/1//COMMIT_MSG@11 
PS1, Line 11: tigerlake
> Tiger Lake

Done

https://review.coreboot.org/c/coreboot/+/38737/3/src/soc/intel/tigerlake/chi... 
File src/soc/intel/tigerlake/chip.h:

https://review.coreboot.org/c/coreboot/+/38737/3/src/soc/intel/tigerlake/chi... 
PS3, Line 235: USB4/TBT
> This is a different config than ITbtPcieRootPortEn... […]

Done

https://review.coreboot.org/c/coreboot/+/38737/4/src/soc/intel/tigerlake/rom... 
File src/soc/intel/tigerlake/romstage/fsp_params_tgl.c:

https://review.coreboot.org/c/coreboot/+/38737/4/src/soc/intel/tigerlake/rom... 
PS4, Line 125: 	m_cfg->TcssItbtPcie0En = config->TcssItbtPcie0En;
             : 	m_cfg->TcssItbtPcie1En = config->TcssItbtPcie1En;
             : 	m_cfg->TcssItbtPcie2En = config->TcssItbtPcie2En;
             : 	m_cfg->TcssItbtPcie3En = config->TcssItbtPcie3En;
             :
> we can but I was under the impression that this was a different setting and a loop really isn't usef […]

Done

Change in coreboot[master]: soc/intel/tigerlake: Update FSP UPDs to turn on USB4/TBT

[Brandon Breitenstein (Code Review)]

Hello build bot (Jenkins), Furquan Shaikh, Caveh Jalali, Paul Menzel, Nick Vaccaro, Tim Wawrzynczak, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/38737

to look at the new patch set (#7).

Change subject: soc/intel/tigerlake: Update FSP UPDs to turn on USB4/TBT
......................................................................

soc/intel/tigerlake: Update FSP UPDs to turn on USB4/TBT

FSP needs to know to allow the root ports for USB4/TBT to be enabled
This patch may need additional checks for each board as it might not
be the right thing to turn them all on for every Tiger Lake board.

BUG=b:141609883
BRANCH=NONE
TEST=Built image and verified that the root ports were visible with lspci

Change-Id: I3f020e20fa8e9fd1ac69d883f4dc1fcbb330a3bf
Signed-off-by: Brandon Breitenstein 
---
M src/soc/intel/tigerlake/fsp_params_tgl.c
M src/soc/intel/tigerlake/romstage/fsp_params_tgl.c
2 files changed, 32 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/38737/7

Change in coreboot[master]: soc/intel/tigerlake: Update FSP UPDs to turn on USB4/TBT

[Tim Wawrzynczak (Code Review)]

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38737 )

Change subject: soc/intel/tigerlake: Update FSP UPDs to turn on USB4/TBT
......................................................................

Patch Set 7: Code-Review+2

Change in coreboot[master]: soc/intel/tigerlake: Update FSP UPDs to turn on USB4/TBT

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/38737 )

Change subject: soc/intel/tigerlake: Update FSP UPDs to turn on USB4/TBT
......................................................................

soc/intel/tigerlake: Update FSP UPDs to turn on USB4/TBT

FSP needs to know to allow the root ports for USB4/TBT to be enabled
This patch may need additional checks for each board as it might not
be the right thing to turn them all on for every Tiger Lake board.

BUG=b:141609883
BRANCH=NONE
TEST=Built image and verified that the root ports were visible with lspci

Change-Id: I3f020e20fa8e9fd1ac69d883f4dc1fcbb330a3bf
Signed-off-by: Brandon Breitenstein 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38737
Tested-by: build bot (Jenkins) 
Reviewed-by: Tim Wawrzynczak 
---
M src/soc/intel/tigerlake/fsp_params_tgl.c
M src/soc/intel/tigerlake/romstage/fsp_params_tgl.c
2 files changed, 32 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Tim Wawrzynczak: Looks good to me, approved

diff --git a/src/soc/intel/tigerlake/fsp_params_tgl.c b/src/soc/intel/tigerlake/fsp_params_tgl.c
index f3f700f..a8be407 100644
--- a/src/soc/intel/tigerlake/fsp_params_tgl.c
+++ b/src/soc/intel/tigerlake/fsp_params_tgl.c
@@ -186,6 +186,15 @@
    /* Enable Hybrid storage auto detection */
    params->HybridStorageMode = config->HybridStorageMode;

+	/* USB4/TBT */
+	for (i = 0; i < ARRAY_SIZE(params->ITbtPcieRootPortEn); i++) {
+		dev = pcidev_on_root(SA_DEV_SLOT_TBT, i);
+		if (dev)
+			params->ITbtPcieRootPortEn[i] = dev->enabled;
+		else
+			params->ITbtPcieRootPortEn[i] = 0;
+	}
+
    mainboard_silicon_init_params(params);
 }

diff --git a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c
index e275e59..95f637e 100644
--- a/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c
+++ b/src/soc/intel/tigerlake/romstage/fsp_params_tgl.c
@@ -120,6 +120,29 @@
    m_cfg->TcssXhciEn = config->TcssXhciEn;
    m_cfg->TcssXdciEn = config->TcssXdciEn;

+	/* USB4/TBT */
+	dev = pcidev_path_on_root(SA_DEVFN_TBT0);
+	if (dev)
+		m_cfg->TcssItbtPcie0En = dev->enabled;
+	else
+		m_cfg->TcssItbtPcie0En = 0;
+	dev = pcidev_path_on_root(SA_DEVFN_TBT1);
+	if (dev)
+		m_cfg->TcssItbtPcie1En = dev->enabled;
+	else
+		m_cfg->TcssItbtPcie1En = 0;
+
+	dev = pcidev_path_on_root(SA_DEVFN_TBT2);
+	if (dev)
+		m_cfg->TcssItbtPcie2En = dev->enabled;
+	else
+		m_cfg->TcssItbtPcie2En = 0;
+	dev = pcidev_path_on_root(SA_DEVFN_TBT3);
+	if (dev)
+		m_cfg->TcssItbtPcie3En = dev->enabled;
+	else
+		m_cfg->TcssItbtPcie3En = 0;
+
    /* Enable Hyper Threading */
    m_cfg->HyperThreading = 1;
    /* Disable Lock PCU Thermal Management registers */