New patch to review for coreboot: 032e17b exynos5420: Switch to fixed size types in dmc.h.
Gabe Black (gabeblack@chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3685
-gerrit
commit 032e17bd0a191691185f3711e0eb3579794247e3 Author: Gabe Black gabeblack@google.com Date: Wed Jun 19 01:37:59 2013 -0700
exynos5420: Switch to fixed size types in dmc.h.
The members data structures in dmc.h are intended to have a particular size. Rather than assume that particular types are the right size, we should use types that are guaranteed to be the right size. Also, since the registers are at particular offsets as well, the structures should be packed.
Change-Id: I9cc11d7451f92ba3eb85c6be88ecbc62c7a5652d Signed-off-by: Gabe Black gabeblack@chromium.org --- src/cpu/samsung/exynos5420/dmc.h | 366 +++++++++++++++++++-------------------- 1 file changed, 183 insertions(+), 183 deletions(-)
diff --git a/src/cpu/samsung/exynos5420/dmc.h b/src/cpu/samsung/exynos5420/dmc.h index df7797d..c974db2 100644 --- a/src/cpu/samsung/exynos5420/dmc.h +++ b/src/cpu/samsung/exynos5420/dmc.h @@ -70,193 +70,193 @@
#ifndef __ASSEMBLER__ struct exynos5_dmc { - unsigned int concontrol; - unsigned int memcontrol; - unsigned int cgcontrol; - unsigned int memconfig1; - unsigned int directcmd; - unsigned int prechconfig0; - unsigned int phycontrol0; - unsigned int prechconfig1; - unsigned char res1[0x8]; - unsigned int pwrdnconfig; /* 0x0028*/ - unsigned int timingpzq; - unsigned int timingref; - unsigned int timingrow; - unsigned int timingdata; - unsigned int timingpower; - unsigned int phystatus; - unsigned char res2[0x4]; - unsigned int chipstatus_ch0; /* 0x0048 */ - unsigned int chipstatus_ch1; - unsigned char res3[0x4]; - unsigned int mrstatus; - unsigned char res4[0x8]; - unsigned int qoscontrol0; /* 0x0060 */ - unsigned char resr5[0x4]; - unsigned int qoscontrol1; - unsigned char res6[0x4]; - unsigned int qoscontrol2; - unsigned char res7[0x4]; - unsigned int qoscontrol3; - unsigned char res8[0x4]; - unsigned int qoscontrol4; - unsigned char res9[0x4]; - unsigned int qoscontrol5; - unsigned char res10[0x4]; - unsigned int qoscontrol6; - unsigned char res11[0x4]; - unsigned int qoscontrol7; - unsigned char res12[0x4]; - unsigned int qoscontrol8; - unsigned char res13[0x4]; - unsigned int qoscontrol9; - unsigned char res14[0x4]; - unsigned int qoscontrol10; - unsigned char res15[0x4]; - unsigned int qoscontrol11; - unsigned char res16[0x4]; - unsigned int qoscontrol12; - unsigned char res17[0x4]; - unsigned int qoscontrol13; - unsigned char res18[0x4]; - unsigned int qoscontrol14; - unsigned char res19[0x4]; - unsigned int qoscontrol15; - unsigned char res20[0x4]; - unsigned int timing_set_sw; /* 0x00e0 */ - unsigned int timingrow1; - unsigned int timingdata1; - unsigned int timingpower1; - unsigned int ivcontrol; - unsigned int wrtra_config; - unsigned int rdlvl_config; - unsigned char res21[0x4]; - unsigned int brbrsvcontrol; /* 0x0100*/ - unsigned int brbrsvconfig; - unsigned int brbqosconfig; - unsigned int membaseconfig0; - unsigned int membaseconfig1; /* 0x0110 */ - unsigned char res22[0xc]; - unsigned int wrlvl_config0; /* 0x0120 */ - unsigned int wrlvl_config1; - unsigned int wrlvl_status; - unsigned char res23[0x4]; - unsigned int perevcontrol; /* 0x0130 */ - unsigned int perev0config; - unsigned int perev1config; - unsigned int perev2config; - unsigned int perev3config; - unsigned char res22a[0xc]; - unsigned int ctrl_io_rdata_ch0; - unsigned int ctrl_io_rdata_ch1; - unsigned char res23a[0x8]; - unsigned int cacal_config0; - unsigned int cacal_config1; - unsigned int cacal_status; - unsigned char res24[0x94]; - unsigned int emergent_config0; /* 0x0200 */ - unsigned int emergent_config1; - unsigned char res25[0x8]; - unsigned int bp_control0; - unsigned int bp_control0_r; - unsigned int bp_control0_w; - unsigned char res26[0x4]; - unsigned int bp_control1; - unsigned int bp_control1_r; - unsigned int bp_control1_w; - unsigned char res27[0x4]; - unsigned int bp_control2; - unsigned int bp_control2_r; - unsigned int bp_control2_w; - unsigned char res28[0x4]; - unsigned int bp_control3; - unsigned int bp_control3_r; - unsigned int bp_control3_w; - unsigned char res29[0xb4]; - unsigned int winconfig_odt_w; /* 0x0300 */ - unsigned char res30[0x4]; - unsigned int winconfig_ctrl_read; - unsigned int winconfig_ctrl_gate; - unsigned char res31[0xdcf0]; - unsigned int pmnc_ppc; - unsigned char res32[0xc]; - unsigned int cntens_ppc; - unsigned char res33[0xc]; - unsigned int cntenc_ppc; - unsigned char res34[0xc]; - unsigned int intens_ppc; - unsigned char res35[0xc]; - unsigned int intenc_ppc; - unsigned char res36[0xc]; - unsigned int flag_ppc; /* 0xe050 */ - unsigned char res37[0xac]; - unsigned int ccnt_ppc; - unsigned char res38[0xc]; - unsigned int pmcnt0_ppc; - unsigned char res39[0xc]; - unsigned int pmcnt1_ppc; - unsigned char res40[0xc]; - unsigned int pmcnt2_ppc; - unsigned char res41[0xc]; - unsigned int pmcnt3_ppc; /* 0xe140 */ -}; + uint32_t concontrol; + uint32_t memcontrol; + uint32_t cgcontrol; + uint32_t memconfig1; + uint32_t directcmd; + uint32_t prechconfig0; + uint32_t phycontrol0; + uint32_t prechconfig1; + uint8_t res1[0x8]; + uint32_t pwrdnconfig; /* 0x0028*/ + uint32_t timingpzq; + uint32_t timingref; + uint32_t timingrow; + uint32_t timingdata; + uint32_t timingpower; + uint32_t phystatus; + uint8_t res2[0x4]; + uint32_t chipstatus_ch0; /* 0x0048 */ + uint32_t chipstatus_ch1; + uint8_t res3[0x4]; + uint32_t mrstatus; + uint8_t res4[0x8]; + uint32_t qoscontrol0; /* 0x0060 */ + uint8_t resr5[0x4]; + uint32_t qoscontrol1; + uint8_t res6[0x4]; + uint32_t qoscontrol2; + uint8_t res7[0x4]; + uint32_t qoscontrol3; + uint8_t res8[0x4]; + uint32_t qoscontrol4; + uint8_t res9[0x4]; + uint32_t qoscontrol5; + uint8_t res10[0x4]; + uint32_t qoscontrol6; + uint8_t res11[0x4]; + uint32_t qoscontrol7; + uint8_t res12[0x4]; + uint32_t qoscontrol8; + uint8_t res13[0x4]; + uint32_t qoscontrol9; + uint8_t res14[0x4]; + uint32_t qoscontrol10; + uint8_t res15[0x4]; + uint32_t qoscontrol11; + uint8_t res16[0x4]; + uint32_t qoscontrol12; + uint8_t res17[0x4]; + uint32_t qoscontrol13; + uint8_t res18[0x4]; + uint32_t qoscontrol14; + uint8_t res19[0x4]; + uint32_t qoscontrol15; + uint8_t res20[0x4]; + uint32_t timing_set_sw; /* 0x00e0 */ + uint32_t timingrow1; + uint32_t timingdata1; + uint32_t timingpower1; + uint32_t ivcontrol; + uint32_t wrtra_config; + uint32_t rdlvl_config; + uint8_t res21[0x4]; + uint32_t brbrsvcontrol; /* 0x0100*/ + uint32_t brbrsvconfig; + uint32_t brbqosconfig; + uint32_t membaseconfig0; + uint32_t membaseconfig1; /* 0x0110 */ + uint8_t res22[0xc]; + uint32_t wrlvl_config0; /* 0x0120 */ + uint32_t wrlvl_config1; + uint32_t wrlvl_status; + uint8_t res23[0x4]; + uint32_t perevcontrol; /* 0x0130 */ + uint32_t perev0config; + uint32_t perev1config; + uint32_t perev2config; + uint32_t perev3config; + uint8_t res22a[0xc]; + uint32_t ctrl_io_rdata_ch0; + uint32_t ctrl_io_rdata_ch1; + uint8_t res23a[0x8]; + uint32_t cacal_config0; + uint32_t cacal_config1; + uint32_t cacal_status; + uint8_t res24[0x94]; + uint32_t emergent_config0; /* 0x0200 */ + uint32_t emergent_config1; + uint8_t res25[0x8]; + uint32_t bp_control0; + uint32_t bp_control0_r; + uint32_t bp_control0_w; + uint8_t res26[0x4]; + uint32_t bp_control1; + uint32_t bp_control1_r; + uint32_t bp_control1_w; + uint8_t res27[0x4]; + uint32_t bp_control2; + uint32_t bp_control2_r; + uint32_t bp_control2_w; + uint8_t res28[0x4]; + uint32_t bp_control3; + uint32_t bp_control3_r; + uint32_t bp_control3_w; + uint8_t res29[0xb4]; + uint32_t winconfig_odt_w; /* 0x0300 */ + uint8_t res30[0x4]; + uint32_t winconfig_ctrl_read; + uint32_t winconfig_ctrl_gate; + uint8_t res31[0xdcf0]; + uint32_t pmnc_ppc; + uint8_t res32[0xc]; + uint32_t cntens_ppc; + uint8_t res33[0xc]; + uint32_t cntenc_ppc; + uint8_t res34[0xc]; + uint32_t intens_ppc; + uint8_t res35[0xc]; + uint32_t intenc_ppc; + uint8_t res36[0xc]; + uint32_t flag_ppc; /* 0xe050 */ + uint8_t res37[0xac]; + uint32_t ccnt_ppc; + uint8_t res38[0xc]; + uint32_t pmcnt0_ppc; + uint8_t res39[0xc]; + uint32_t pmcnt1_ppc; + uint8_t res40[0xc]; + uint32_t pmcnt2_ppc; + uint8_t res41[0xc]; + uint32_t pmcnt3_ppc; /* 0xe140 */ +} __attribute__((packed));
struct exynos5_phy_control { - unsigned int phy_con0; - unsigned int phy_con1; - unsigned int phy_con2; - unsigned int phy_con3; - unsigned int phy_con4; - unsigned char res1[4]; - unsigned int phy_con6; - unsigned char res2[4]; - unsigned int phy_con8; - unsigned int phy_con9; - unsigned int phy_con10; - unsigned char res3[4]; - unsigned int phy_con12; - unsigned int phy_con13; - unsigned int phy_con14; - unsigned int phy_con15; - unsigned int phy_con16; - unsigned char res4[4]; - unsigned int phy_con17; - unsigned int phy_con18; - unsigned int phy_con19; - unsigned int phy_con20; - unsigned int phy_con21; - unsigned int phy_con22; - unsigned int phy_con23; - unsigned int phy_con24; - unsigned int phy_con25; - unsigned int phy_con26; - unsigned int phy_con27; - unsigned int phy_con28; - unsigned int phy_con29; - unsigned int phy_con30; - unsigned int phy_con31; - unsigned int phy_con32; - unsigned int phy_con33; - unsigned int phy_con34; - unsigned int phy_con35; - unsigned int phy_con36; - unsigned int phy_con37; - unsigned int phy_con38; - unsigned int phy_con39; - unsigned int phy_con40; - unsigned int phy_con41; - unsigned int phy_con42; -}; + uint32_t phy_con0; + uint32_t phy_con1; + uint32_t phy_con2; + uint32_t phy_con3; + uint32_t phy_con4; + uint8_t res1[4]; + uint32_t phy_con6; + uint8_t res2[4]; + uint32_t phy_con8; + uint32_t phy_con9; + uint32_t phy_con10; + uint8_t res3[4]; + uint32_t phy_con12; + uint32_t phy_con13; + uint32_t phy_con14; + uint32_t phy_con15; + uint32_t phy_con16; + uint8_t res4[4]; + uint32_t phy_con17; + uint32_t phy_con18; + uint32_t phy_con19; + uint32_t phy_con20; + uint32_t phy_con21; + uint32_t phy_con22; + uint32_t phy_con23; + uint32_t phy_con24; + uint32_t phy_con25; + uint32_t phy_con26; + uint32_t phy_con27; + uint32_t phy_con28; + uint32_t phy_con29; + uint32_t phy_con30; + uint32_t phy_con31; + uint32_t phy_con32; + uint32_t phy_con33; + uint32_t phy_con34; + uint32_t phy_con35; + uint32_t phy_con36; + uint32_t phy_con37; + uint32_t phy_con38; + uint32_t phy_con39; + uint32_t phy_con40; + uint32_t phy_con41; + uint32_t phy_con42; +} __attribute__((packed));
struct exynos5_tzasc { - unsigned char res1[0xf00]; - unsigned int membaseconfig0; - unsigned int membaseconfig1; - unsigned char res2[0x8]; - unsigned int memconfig0; - unsigned int memconfig1; -}; + uint8_t res1[0xf00]; + uint32_t membaseconfig0; + uint32_t membaseconfig1; + uint8_t res2[0x8]; + uint32_t memconfig0; + uint32_t memconfig1; +} __attribute__((packed));
enum ddr_mode { DDR_MODE_DDR2,
-
Gabe Black