Change in coreboot[master]: soc/intel/skylake: vr_config: enable PSI3 and PSI4 by default

[Matt DeVillier (Code Review)]

Matt DeVillier has uploaded a new patch set (#6) to the change originally created by Michael Niewöhner. ( https://review.coreboot.org/c/coreboot/+/39980 )

Change subject: soc/intel/skylake: vr_config: enable PSI3 and PSI4 by default
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soc/intel/skylake: vr_config: enable PSI3 and PSI4 by default

There are boards that do not need a specific domain_vr_config because
the defaults provided by the soc code are sufficient. Currently, this
means that these boards can't benefit from lower power states (PSI 3
and 4) because the settings default to being disabled.

Set the default values of psiXenable to 1 for boards that do not have a
domain_vr_config setting in their devicetree, just like Cannon Lake
does.

Boards that have a domain_vr_config and set their specific settings are
not affected at all. Currently, there are only three boards that have
no domain_vr_config:

- supermicro/x11-lga1151-series/variants/x11ssm-f:
  Tested successfully with PSI3/4 enabled.

- supermicro/x11-lga1151-series/variants/x11ssh-tf:
  Needs testing. This board is mostly identical to x11ssm-f and thus is
  expected to just work fine.

- 51nb/x210:
  Needs testing.

Change-Id: I5b5fd9fb3b9b89e80c47f15d706e2dd62dcc0748
Signed-off-by: Michael Niewöhner 
---
M src/soc/intel/skylake/vr_config.c
1 file changed, 8 insertions(+), 8 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/39980/6