Change in coreboot[master]: soc/intel/alderlake: Disable VT-d for early silicons - coreboot-gerrit

12 Nov 2021


      Attention is currently required from: Abhijeet Rao, Maulik V Vaghela, Meera Ravindranath, Patrick Rudolph.
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59191 )
Change subject: soc/intel/alderlake: Disable VT-d for early silicons
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Patch Set 6: Code-Review+2
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I0b9b76b6527d8b80777cb7588ce6b12282af7882
Gerrit-Change-Number: 59191
Gerrit-PatchSet: 6
Gerrit-Owner: Meera Ravindranath meera.ravindranath@intel.com
Gerrit-Reviewer:  Felix Singer felixsinger@posteo.net
Gerrit-Reviewer: Abhijeet Rao abhijeet.rao@intel.corp-partner.google.com
Gerrit-Reviewer: Maulik V Vaghela maulik.v.vaghela@intel.com
Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org
Gerrit-Reviewer: Tim Wawrzynczak twawrzynczak@chromium.org
Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org
Gerrit-Attention: Abhijeet Rao abhijeet.rao@intel.corp-partner.google.com
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Gerrit-Attention: Meera Ravindranath meera.ravindranath@intel.com
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Gerrit-Comment-Date: Fri, 12 Nov 2021 16:59:21 +0000
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