Change in coreboot[master]: skylake DDR4 boards: Set `CaVrefConfig` to 2

[Angel Pons (Code Review)]

Attention is currently required from: Nico Huber, Frans Hendriks, Matt DeVillier, Arthur Heymans, Michael Niewöhner, Patrick Rudolph, Wim Vervoorn.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57262 )

Change subject: skylake DDR4 boards: Set `CaVrefConfig` to 2
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Patch Set 3:

(1 comment)

File src/mainboard/kontron/bsl6/romstage.c:

https://review.coreboot.org/c/coreboot/+/57262/comment/c5f419cb_288a66a6 
PS3, Line 40: 	memory_params->CaVrefConfig = 2;
> Hmmm, I was much surprised to see that we didn't query Kontron about this […]

If you have schematics, it's very easy to check what the correct value is. I wrote a very long comment in CB:52110 that should explain what to look for.

With `CaVrefConfig` set to 0 on DDR4, MRC still adjusts write Vref correctly, but sometimes skips configuring CA (Command/Address) Vref for channel 1. I didn't observe any significant differences in my tests on 1DPC (DPC = DIMM Per Channel) configurations, as CA margins are pretty large. However, there could be issues with 2DPC configurations (margins aren't as good).

TL;DR: I don't expect this change to make any noticeable difference, especially on this particular board.