Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43410 )
Change subject: mb/51nb/x210/gpio: Convert configuration to macros ......................................................................
mb/51nb/x210/gpio: Convert configuration to macros
Use the intelp2m utility [1,2] to convert the current pad configuration format to the format with the the PAD_CFG*() macros (*).
$ ./intelp2m -n -t 1 -p snr -file src/mainboard/51nb/x210/gpio.h
Unlike the raw DW0 and DW1 registers values from the inteltool dump, is more understandable and makes the code much cleaner.
[*] To do this, ignore some bit fields. See ...
Change-Id: I18c0c321561eee04ff927681b0a231f6d79c63e2 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/mainboard/51nb/x210/gpio.h 1 file changed, 164 insertions(+), 164 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/43410/1
diff --git a/src/mainboard/51nb/x210/gpio.h b/src/mainboard/51nb/x210/gpio.h index c517b44..d6f164e 100644 --- a/src/mainboard/51nb/x210/gpio.h +++ b/src/mainboard/51nb/x210/gpio.h @@ -10,170 +10,170 @@
/* Pad configuration in ramstage. */ static const struct pad_config gpio_table[] = { -/* RCIN# */_PAD_CFG_STRUCT(GPP_A0, 0x44000702, 0x0), -/* LAD0 */_PAD_CFG_STRUCT(GPP_A1, 0x44000702, 0x3c00), -/* LAD1 */_PAD_CFG_STRUCT(GPP_A2, 0x44000702, 0x3c00), -/* LAD2 */_PAD_CFG_STRUCT(GPP_A3, 0x44000702, 0x3c00), -/* LAD3 */_PAD_CFG_STRUCT(GPP_A4, 0x44000702, 0x3c00), -/* LFRAME# */_PAD_CFG_STRUCT(GPP_A5, 0x44000700, 0x0), -/* SERIRQ */_PAD_CFG_STRUCT(GPP_A6, 0x44000702, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_A7, 0x44000201, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_A8, 0x44000300, 0x3000), -/* CLKOUT_LPC0 */_PAD_CFG_STRUCT(GPP_A9, 0x44000700, 0x1000), -/* CLKOUT_LPC1 */_PAD_CFG_STRUCT(GPP_A10, 0x44000700, 0x1000), -/* GPIO */_PAD_CFG_STRUCT(GPP_A11, 0x44000200, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_A12, 0x4000200, 0x0), -/* SUSWARN#/SUSPWRDNACK */_PAD_CFG_STRUCT(GPP_A13, 0x44000700, 0x0), -/* SUS_STAT# */_PAD_CFG_STRUCT(GPP_A14, 0x44000700, 0x0), -/* SUS_ACK# */_PAD_CFG_STRUCT(GPP_A15, 0x44000702, 0x3000), -/* CLKOUT_48 */_PAD_CFG_STRUCT(GPP_A16, 0x44000500, 0x0), -/* ISH_GP7 */_PAD_CFG_STRUCT(GPP_A17, 0x44000700, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_A18, 0x44000300, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_A19, 0x44000300, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_A20, 0x44000300, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_A21, 0x44000300, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_A22, 0x44000201, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_A23, 0x44000100, 0x1000), -/* n/a */_PAD_CFG_STRUCT(GPP_B0, 0x44000700, 0x0), -/* n/a */_PAD_CFG_STRUCT(GPP_B1, 0x44000700, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_B2, 0x44000300, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_B3, 0x84000102, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_B4, 0x44000201, 0x0), -/* SRCCLKREQ0# */_PAD_CFG_STRUCT(GPP_B5, 0x44000700, 0x0), -/* SRCCLKREQ1# */_PAD_CFG_STRUCT(GPP_B6, 0x44000700, 0x0), -/* SRCCLKREQ2# */_PAD_CFG_STRUCT(GPP_B7, 0x44000702, 0x0), -/* SRCCLKREQ3# */_PAD_CFG_STRUCT(GPP_B8, 0x44000702, 0x0), -/* SRCCLKREQ4# */_PAD_CFG_STRUCT(GPP_B9, 0x44000700, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_B10, 0x44000102, 0x0), -/* n/a */_PAD_CFG_STRUCT(GPP_B11, 0x44000700, 0x0), -/* SLP_S0# */_PAD_CFG_STRUCT(GPP_B12, 0x44000700, 0x0), -/* PLTRST# */_PAD_CFG_STRUCT(GPP_B13, 0x44000700, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_B14, 0x44000201, 0x1000), -/* GPIO */_PAD_CFG_STRUCT(GPP_B15, 0x44000300, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_B16, 0x84800102, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_B17, 0x84800102, 0x3000), -/* GPIO */_PAD_CFG_STRUCT(GPP_B18, 0x84800102, 0x3000), -/* GPIO */_PAD_CFG_STRUCT(GPP_B19, 0x44000300, 0x0), -/* GSPI1_CLK */_PAD_CFG_STRUCT(GPP_B20, 0x44000700, 0x1000), -/* GSPI1_MISO */_PAD_CFG_STRUCT(GPP_B21, 0x44000700, 0x1000), -/* GSPIO_MOSI */_PAD_CFG_STRUCT(GPP_B22, 0x44000700, 0x1000), -/* GPIO */_PAD_CFG_STRUCT(GPP_B23, 0x44000201, 0x1000), -/* SMBCLK */_PAD_CFG_STRUCT(GPP_C0, 0x44000702, 0x0), -/* SMBDATA */_PAD_CFG_STRUCT(GPP_C1, 0x44000702, 0x1000), -/* GPIO */_PAD_CFG_STRUCT(GPP_C2, 0x44000201, 0x1000), -/* SML0CLK */_PAD_CFG_STRUCT(GPP_C3, 0x44000702, 0x3000), -/* SML0DATA */_PAD_CFG_STRUCT(GPP_C4, 0x44000702, 0x3000), -/* GPIO */_PAD_CFG_STRUCT(GPP_C5, 0x44800100, 0x1000), -/* RESERVED */_PAD_CFG_STRUCT(GPP_C6, 0xffffffff, 0xffffff00), -/* RESERVED */_PAD_CFG_STRUCT(GPP_C7, 0xffffffff, 0xffffff00), -/* UART0_RXD */_PAD_CFG_STRUCT(GPP_C8, 0x44000702, 0x3000), -/* UART0_TXD */_PAD_CFG_STRUCT(GPP_C9, 0x44000700, 0x0), -/* UART0_RTS# */_PAD_CFG_STRUCT(GPP_C10, 0x44000700, 0x0), -/* UART0_CTS# */_PAD_CFG_STRUCT(GPP_C11, 0x44000702, 0x0), -/* UART1_RXD */_PAD_CFG_STRUCT(GPP_C12, 0x44000702, 0x0), -/* UART1_TXD */_PAD_CFG_STRUCT(GPP_C13, 0x44000700, 0x0), -/* UART1_RTS# */_PAD_CFG_STRUCT(GPP_C14, 0x44000700, 0x0), -/* UART1_CTS# */_PAD_CFG_STRUCT(GPP_C15, 0x44000702, 0x0), -/* I2C0_SDA */_PAD_CFG_STRUCT(GPP_C16, 0x44000702, 0x3000), -/* I2C0_SCL */_PAD_CFG_STRUCT(GPP_C17, 0x44000702, 0x3000), -/* I2C1_SDA */_PAD_CFG_STRUCT(GPP_C18, 0x44000702, 0x3000), -/* I2C1_SCL */_PAD_CFG_STRUCT(GPP_C19, 0x44000702, 0x3000), -/* UART2_RXD */_PAD_CFG_STRUCT(GPP_C20, 0x44000702, 0x3000), -/* UART2_TXD */_PAD_CFG_STRUCT(GPP_C21, 0x44000700, 0x0), -/* UART2_RTS# */_PAD_CFG_STRUCT(GPP_C22, 0x44000700, 0x0), -/* UART2_CTS# */_PAD_CFG_STRUCT(GPP_C23, 0x44000702, 0x0), -/* n/a */_PAD_CFG_STRUCT(GPP_D0, 0x44000700, 0x0), -/* n/a */_PAD_CFG_STRUCT(GPP_D1, 0x44000700, 0x0), -/* n/a */_PAD_CFG_STRUCT(GPP_D2, 0x44000700, 0x0), -/* n/a */_PAD_CFG_STRUCT(GPP_D3, 0x44000700, 0x0), -/* ISH_I2C2_SDA */_PAD_CFG_STRUCT(GPP_D4, 0x44000700, 0x0), -/* I2S_SFRM */_PAD_CFG_STRUCT(GPP_D5, 0x44000702, 0x3000), -/* I2S_TXD */_PAD_CFG_STRUCT(GPP_D6, 0x44000702, 0x3000), -/* I2S_RXD */_PAD_CFG_STRUCT(GPP_D7, 0x44000702, 0x3000), -/* I2S_SCLK */_PAD_CFG_STRUCT(GPP_D8, 0x44000702, 0x3000), -/* GPIO */_PAD_CFG_STRUCT(GPP_D9, 0x44000102, 0x3000), -/* GPIO */_PAD_CFG_STRUCT(GPP_D10, 0x44000102, 0x3000), -/* GPIO */_PAD_CFG_STRUCT(GPP_D11, 0x44000102, 0x3000), -/* GPIO */_PAD_CFG_STRUCT(GPP_D12, 0x44000102, 0x3000), -/* ISH_UART0_RXD */_PAD_CFG_STRUCT(GPP_D13, 0x44000702, 0x3000), -/* ISH_UART0_TXD */_PAD_CFG_STRUCT(GPP_D14, 0x44000700, 0x3000), -/* ISH_UART0_RTS# */_PAD_CFG_STRUCT(GPP_D15, 0x44000700, 0x0), -/* ISH_UART0_CTS# */_PAD_CFG_STRUCT(GPP_D16, 0x44000702, 0x0), -/* DMIC_CLK1 */_PAD_CFG_STRUCT(GPP_D17, 0x44000700, 0x0), -/* DMIC_DATA1 */_PAD_CFG_STRUCT(GPP_D18, 0x44000700, 0x1000), -/* DMIC_CLK0 */_PAD_CFG_STRUCT(GPP_D19, 0x44000700, 0x0), -/* DMIC_DATA0 */_PAD_CFG_STRUCT(GPP_D20, 0x44000700, 0x1000), -/* n/a */_PAD_CFG_STRUCT(GPP_D21, 0x44000700, 0x0), -/* n/a */_PAD_CFG_STRUCT(GPP_D22, 0x44000700, 0x0), -/* ISH_I2C2_SCL */_PAD_CFG_STRUCT(GPP_D23, 0x44000700, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_E0, 0x44000200, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_E1, 0x44800102, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_E2, 0x44000300, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_E3, 0x44000103, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_E4, 0x44000300, 0x0), -/* SATA_DEVSLP1 */_PAD_CFG_STRUCT(GPP_E5, 0x4000700, 0x0), -/* SATA_DEVSLP2 */_PAD_CFG_STRUCT(GPP_E6, 0x4000700, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_E7, 0x44000300, 0x0), -/* SATA_LED# */_PAD_CFG_STRUCT(GPP_E8, 0x44000700, 0x0), -/* USB_OC0# */_PAD_CFG_STRUCT(GPP_E9, 0x44000702, 0x0), -/* USB_OC1# */_PAD_CFG_STRUCT(GPP_E10, 0x44000702, 0x0), -/* USB_OC2# */_PAD_CFG_STRUCT(GPP_E11, 0x44000702, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_E12, 0x44000300, 0x0), -/* n/a */_PAD_CFG_STRUCT(GPP_E13, 0x44000700, 0x0), -/* n/a */_PAD_CFG_STRUCT(GPP_E14, 0x44000700, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_E15, 0x80880102, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_E16, 0x84000102, 0x0), -/* n/a */_PAD_CFG_STRUCT(GPP_E17, 0x44000702, 0x0), -/* n/a */_PAD_CFG_STRUCT(GPP_E18, 0x44000700, 0x3000), -/* n/a */_PAD_CFG_STRUCT(GPP_E19, 0x44000700, 0x1000), -/* n/a */_PAD_CFG_STRUCT(GPP_E20, 0x44000702, 0x3000), -/* n/a */_PAD_CFG_STRUCT(GPP_E21, 0x44000702, 0x1000), -/* GPIO */_PAD_CFG_STRUCT(GPP_E22, 0x44000000, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_E23, 0x44000201, 0x1000), -/* BATLOW# */_PAD_CFG_STRUCT(GPD0, 0x4000702, 0x3000), -/* ACPRESENT */_PAD_CFG_STRUCT(GPD1, 0x4000702, 0x0), -/* LAN_WAKE# */_PAD_CFG_STRUCT(GPD2, 0x4000602, 0x3c00), -/* PWRBTN# */_PAD_CFG_STRUCT(GPD3, 0x4000702, 0x3000), -/* SLP_S3# */_PAD_CFG_STRUCT(GPD4, 0x4000700, 0x0), -/* SLP_S4# */_PAD_CFG_STRUCT(GPD5, 0x4000700, 0x0), -/* SLP_A# */_PAD_CFG_STRUCT(GPD6, 0x4000700, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPD7, 0x4000301, 0x0), -/* SUSCLK */_PAD_CFG_STRUCT(GPD8, 0x4000700, 0x0), -/* SLP_WLAN# */_PAD_CFG_STRUCT(GPD9, 0x4000700, 0x0), -/* SLP_S5# */_PAD_CFG_STRUCT(GPD10, 0x4000700, 0x0), -/* LANPHYPC */_PAD_CFG_STRUCT(GPD11, 0x4000700, 0x0), -/* SATAXPCIE3 */_PAD_CFG_STRUCT(GPP_F0, 0x44000700, 0x0), -/* SATAXPCIE4 */_PAD_CFG_STRUCT(GPP_F1, 0x44000700, 0x0), -/* SATAXPCIE5 */_PAD_CFG_STRUCT(GPP_F2, 0x44000700, 0x0), -/* SATAXPCIE6 */_PAD_CFG_STRUCT(GPP_F3, 0x44000700, 0x0), -/* SATAXPCIE7 */_PAD_CFG_STRUCT(GPP_F4, 0x44000702, 0x2003000), -/* SATA_DEVSLP3 */_PAD_CFG_STRUCT(GPP_F5, 0x44000702, 0x2003000), -/* SATA_DEVSLP4 */_PAD_CFG_STRUCT(GPP_F6, 0x44000702, 0x2003000), -/* SATA_DEVSLP5 */_PAD_CFG_STRUCT(GPP_F7, 0x44000702, 0x2003000), -/* SATA_DEVSLP6 */_PAD_CFG_STRUCT(GPP_F8, 0x44000702, 0x2003000), -/* SATA_DEVSLP7 */_PAD_CFG_STRUCT(GPP_F9, 0x44000702, 0x2003000), -/* n/a */_PAD_CFG_STRUCT(GPP_F10, 0x44000b02, 0x2003000), -/* n/a */_PAD_CFG_STRUCT(GPP_F11, 0x44000b02, 0x2003000), -/* SATA_SDATAOUT1 */_PAD_CFG_STRUCT(GPP_F12, 0x44000700, 0x0), -/* SATA_SDATAOUT2 */_PAD_CFG_STRUCT(GPP_F13, 0x44000700, 0x0), -/* n/a */_PAD_CFG_STRUCT(GPP_F14, 0x44000700, 0x0), -/* USB_OC4# */_PAD_CFG_STRUCT(GPP_F15, 0x44000700, 0x0), -/* USB_OC5# */_PAD_CFG_STRUCT(GPP_F16, 0x44000700, 0x0), -/* USB_OC6# */_PAD_CFG_STRUCT(GPP_F17, 0x44000700, 0x0), -/* USB_OC7# */_PAD_CFG_STRUCT(GPP_F18, 0x44000700, 0x0), -/* eDP_VDDEN */_PAD_CFG_STRUCT(GPP_F19, 0x44000700, 0x0), -/* eDP_BKLTEN */_PAD_CFG_STRUCT(GPP_F20, 0x44000700, 0x0), -/* eDP_BKLTCTL */_PAD_CFG_STRUCT(GPP_F21, 0x44000700, 0x0), -/* n/a */_PAD_CFG_STRUCT(GPP_F22, 0x44000700, 0x0), -/* GPIO */_PAD_CFG_STRUCT(GPP_F23, 0x44000102, 0x0), -/* FAN_TACH_0 */_PAD_CFG_STRUCT(GPP_G0, 0x44000700, 0x0), -/* FAN_TACH_1 */_PAD_CFG_STRUCT(GPP_G1, 0x44000700, 0x0), -/* FAN_TACH_2 */_PAD_CFG_STRUCT(GPP_G2, 0x44000700, 0x0), -/* FAN_TACH_3 */_PAD_CFG_STRUCT(GPP_G3, 0x44000700, 0x0), -/* FAN_TACH_4 */_PAD_CFG_STRUCT(GPP_G4, 0x44000700, 0x0), -/* FAN_TACH_5 */_PAD_CFG_STRUCT(GPP_G5, 0x44000702, 0x0), -/* FAN_TACH_6 */_PAD_CFG_STRUCT(GPP_G6, 0x44000700, 0x0), -/* FAN_TACH_7 */_PAD_CFG_STRUCT(GPP_G7, 0x44000700, 0x1000), +/* RCIN# */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* LAD0 */ PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* LAD1 */ PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* LAD2 */ PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* LAD3 */ PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* LFRAME# */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* GPIO */ PAD_CFG_GPO(GPP_A7, 1, DEEP), +/* GPIO */ PAD_NC(GPP_A8, 20K_PU), +/* CLKOUT_LPC0 */ PAD_CFG_NF(GPP_A9, 20K_PD, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* CLKOUT_LPC1 */ PAD_CFG_NF(GPP_A10, 20K_PD, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* GPIO */ PAD_CFG_GPO(GPP_A11, 0, DEEP), +/* GPIO */ PAD_CFG_GPO(GPP_A12, 0, PWROK), +/* SUSWARN#/SUSPWRDNACK */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SUS_STAT# */ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SUS_ACK# */ PAD_CFG_NF(GPP_A15, 20K_PU, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* CLKOUT_48 */ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) - IGNORED */ +/* ISH_GP7 */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* GPIO */ PAD_NC(GPP_A18, NONE), +/* GPIO */ PAD_NC(GPP_A19, NONE), +/* GPIO */ PAD_NC(GPP_A20, NONE), +/* GPIO */ PAD_NC(GPP_A21, NONE), +/* GPIO */ PAD_CFG_GPO(GPP_A22, 1, DEEP), +/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_A23, 20K_PD, DEEP, OFF, ACPI), +/* n/a */ PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* n/a */ PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* GPIO */ PAD_NC(GPP_B2, NONE), +/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_B3, NONE, PLTRST, OFF, ACPI), +/* GPIO */ PAD_CFG_GPO(GPP_B4, 1, DEEP), +/* SRCCLKREQ0# */ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SRCCLKREQ3# */ PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SRCCLKREQ4# */ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_B10, NONE, DEEP, OFF, ACPI), +/* n/a */ PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* PLTRST# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* GPIO */ PAD_CFG_TERM_GPO(GPP_B14, 1, 20K_PD, DEEP), +/* GPIO */ PAD_NC(GPP_B15, NONE), +/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_B16, NONE, PLTRST, OFF, ACPI), /* (!) DW0 : PAD_RX_POL(INVERT) - IGNORED */ +/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_B17, 20K_PU, PLTRST, OFF, ACPI), /* (!) DW0 : PAD_RX_POL(INVERT) - IGNORED */ +/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_B18, 20K_PU, PLTRST, OFF, ACPI), /* (!) DW0 : PAD_RX_POL(INVERT) - IGNORED */ +/* GPIO */ PAD_NC(GPP_B19, NONE), +/* GSPI1_CLK */ PAD_CFG_NF(GPP_B20, 20K_PD, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* GSPI1_MISO */ PAD_CFG_NF(GPP_B21, 20K_PD, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* GSPIO_MOSI */ PAD_CFG_NF(GPP_B22, 20K_PD, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* GPIO */ PAD_CFG_TERM_GPO(GPP_B23, 1, 20K_PD, DEEP), +/* SMBCLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SMBDATA */ PAD_CFG_NF(GPP_C1, 20K_PD, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* GPIO */ PAD_CFG_TERM_GPO(GPP_C2, 1, 20K_PD, DEEP), +/* SML0CLK */ PAD_CFG_NF(GPP_C3, 20K_PU, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SML0DATA */ PAD_CFG_NF(GPP_C4, 20K_PU, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_C5, 20K_PD, DEEP, OFF, ACPI), /* (!) DW0 : PAD_RX_POL(INVERT) - IGNORED */ +/* RESERVED - GPP_C6 */ +/* RESERVED - GPP_C7 */ +/* UART0_RXD */ PAD_CFG_NF(GPP_C8, 20K_PU, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* UART0_RTS# */ PAD_CFG_NF(GPP_C10, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* UART0_CTS# */ PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* UART1_RXD */ PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* UART1_TXD */ PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* UART1_RTS# */ PAD_CFG_NF(GPP_C14, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* UART1_CTS# */ PAD_CFG_NF(GPP_C15, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* I2C0_SDA */ PAD_CFG_NF(GPP_C16, 20K_PU, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* I2C0_SCL */ PAD_CFG_NF(GPP_C17, 20K_PU, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* I2C1_SDA */ PAD_CFG_NF(GPP_C18, 20K_PU, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* I2C1_SCL */ PAD_CFG_NF(GPP_C19, 20K_PU, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* UART2_RXD */ PAD_CFG_NF(GPP_C20, 20K_PU, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* UART2_RTS# */ PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* UART2_CTS# */ PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* n/a */ PAD_CFG_NF(GPP_D0, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* n/a */ PAD_CFG_NF(GPP_D1, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* n/a */ PAD_CFG_NF(GPP_D2, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* n/a */ PAD_CFG_NF(GPP_D3, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* ISH_I2C2_SDA */ PAD_CFG_NF(GPP_D4, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* I2S_SFRM */ PAD_CFG_NF(GPP_D5, 20K_PU, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* I2S_TXD */ PAD_CFG_NF(GPP_D6, 20K_PU, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* I2S_RXD */ PAD_CFG_NF(GPP_D7, 20K_PU, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* I2S_SCLK */ PAD_CFG_NF(GPP_D8, 20K_PU, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_D9, 20K_PU, DEEP, OFF, ACPI), +/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_D10, 20K_PU, DEEP, OFF, ACPI), +/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_D11, 20K_PU, DEEP, OFF, ACPI), +/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_D12, 20K_PU, DEEP, OFF, ACPI), +/* ISH_UART0_RXD */ PAD_CFG_NF(GPP_D13, 20K_PU, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* ISH_UART0_TXD */ PAD_CFG_NF(GPP_D14, 20K_PU, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* ISH_UART0_RTS# */ PAD_CFG_NF(GPP_D15, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* ISH_UART0_CTS# */ PAD_CFG_NF(GPP_D16, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* DMIC_CLK1 */ PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* DMIC_DATA1 */ PAD_CFG_NF(GPP_D18, 20K_PD, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* DMIC_CLK0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* DMIC_DATA0 */ PAD_CFG_NF(GPP_D20, 20K_PD, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* n/a */ PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* n/a */ PAD_CFG_NF(GPP_D22, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* ISH_I2C2_SCL */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* GPIO */ PAD_CFG_GPO(GPP_E0, 0, DEEP), +/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_E1, NONE, DEEP, OFF, ACPI), /* (!) DW0 : PAD_RX_POL(INVERT) - IGNORED */ +/* GPIO */ PAD_NC(GPP_E2, NONE), +/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_E3, NONE, DEEP, OFF, ACPI), /* (!) DW0 : 1 - IGNORED */ +/* GPIO */ PAD_NC(GPP_E4, NONE), +/* SATA_DEVSLP1 */ PAD_CFG_NF(GPP_E5, NONE, PWROK, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SATA_DEVSLP2 */ PAD_CFG_NF(GPP_E6, NONE, PWROK, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* GPIO */ PAD_NC(GPP_E7, NONE), +/* SATA_LED# */ PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* USB_OC0# */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* USB_OC1# */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* USB_OC2# */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* GPIO */ PAD_NC(GPP_E12, NONE), +/* n/a */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* n/a */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* GPIO */ PAD_CFG_GPI_SCI(GPP_E15, NONE, PLTRST, LEVEL, INVERT), +/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_E16, NONE, PLTRST, OFF, ACPI), +/* n/a */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* n/a */ PAD_CFG_NF(GPP_E18, 20K_PU, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* n/a */ PAD_CFG_NF(GPP_E19, 20K_PD, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* n/a */ PAD_CFG_NF(GPP_E20, 20K_PU, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* n/a */ PAD_CFG_NF(GPP_E21, 20K_PD, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* GPIO */ PAD_CFG_GPIO_BIDIRECT(GPP_E22, 0, NONE, DEEP, OFF, ACPI), +/* GPIO */ PAD_CFG_TERM_GPO(GPP_E23, 1, 20K_PD, DEEP), +/* BATLOW# */ PAD_CFG_NF(GPD0, 20K_PU, PWROK, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* ACPRESENT */ PAD_CFG_NF(GPD1, NONE, PWROK, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* LAN_WAKE# */ PAD_CFG_NF(GPD2, NATIVE, PWROK, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) - IGNORED */ +/* PWRBTN# */ PAD_CFG_NF(GPD3, 20K_PU, PWROK, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SLP_S3# */ PAD_CFG_NF(GPD4, NONE, PWROK, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SLP_S4# */ PAD_CFG_NF(GPD5, NONE, PWROK, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SLP_A# */ PAD_CFG_NF(GPD6, NONE, PWROK, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* GPIO */ PAD_NC(GPD7, NONE), /* (!) DW0 : 1 - IGNORED */ +/* SUSCLK */ PAD_CFG_NF(GPD8, NONE, PWROK, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SLP_WLAN# */ PAD_CFG_NF(GPD9, NONE, PWROK, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SLP_S5# */ PAD_CFG_NF(GPD10, NONE, PWROK, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* LANPHYPC */ PAD_CFG_NF(GPD11, NONE, PWROK, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SATAXPCIE3 */ PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SATAXPCIE4 */ PAD_CFG_NF(GPP_F1, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SATAXPCIE5 */ PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SATAXPCIE6 */ PAD_CFG_NF(GPP_F3, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SATAXPCIE7 */ PAD_CFG_NF(GPP_F4, 20K_PU, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SATA_DEVSLP3 */ PAD_CFG_NF(GPP_F5, 20K_PU, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SATA_DEVSLP4 */ PAD_CFG_NF(GPP_F6, 20K_PU, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SATA_DEVSLP5 */ PAD_CFG_NF(GPP_F7, 20K_PU, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SATA_DEVSLP6 */ PAD_CFG_NF(GPP_F8, 20K_PU, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SATA_DEVSLP7 */ PAD_CFG_NF(GPP_F9, 20K_PU, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* n/a */ PAD_CFG_NF(GPP_F10, 20K_PU, DEEP, NF2), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* n/a */ PAD_CFG_NF(GPP_F11, 20K_PU, DEEP, NF2), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SATA_SDATAOUT1 */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* SATA_SDATAOUT2 */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* n/a */ PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* USB_OC4# */ PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* USB_OC5# */ PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* USB_OC6# */ PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* USB_OC7# */ PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* eDP_VDDEN */ PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* eDP_BKLTEN */ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* eDP_BKLTCTL */ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* n/a */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_F23, NONE, DEEP, OFF, ACPI), +/* FAN_TACH_0 */ PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* FAN_TACH_1 */ PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* FAN_TACH_2 */ PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* FAN_TACH_3 */ PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* FAN_TACH_4 */ PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* FAN_TACH_5 */ PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* FAN_TACH_6 */ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ +/* FAN_TACH_7 */ PAD_CFG_NF(GPP_G7, 20K_PD, DEEP, NF1), /* (!) DW0 : PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ };
#endif
Maxim Polyakov has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/43410 )
Change subject: mb/51nb/x210/gpio: Convert configuration to macros ......................................................................
mb/51nb/x210/gpio: Convert configuration to macros
Use the intelp2m utility [1,2] to convert the current pad configuration format to the format with the the PAD_CFG() macros (*).
$ ./intelp2m -n -t 1 -p snr -file src/mainboard/51nb/x210/gpio.h
Unlike the raw DW0 and DW1 registers values from the inteltool dump, is more understandable and makes the code much cleaner.
[*] To do this, ignore some bit fields. See Patchset 1 | 86b3146261: https://review.coreboot.org/c/coreboot/+/43410/1
Change-Id: I18c0c321561eee04ff927681b0a231f6d79c63e2 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/mainboard/51nb/x210/gpio.h 1 file changed, 164 insertions(+), 164 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/43410/2
Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43410 )
Change subject: mb/51nb/x210/gpio: Convert configuration to macros ......................................................................
Patch Set 3:
thinking out loud: would it make more sense to drop the invalid config bits from the raw values first, then convert the "corrected" raw values to macros cleanly?
Hello build bot (Jenkins), Nico Huber, Matt DeVillier, Paul Menzel, Angel Pons, Michael Niewöhner,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43410
to look at the new patch set (#5).
Change subject: mb/51nb/x210/gpio: Convert configuration to macros ......................................................................
mb/51nb/x210/gpio: Convert configuration to macros
Use the intelp2m utility [1,2] to convert the current pad configuration format to the format with the the PAD_CFG() macros (*).
$ ./intelp2m -n -t 1 -p snr -file src/mainboard/51nb/x210/gpio.h
Unlike the raw DW0 and DW1 registers values from the inteltool dump, is more understandable and makes the code much cleaner.
[*] To do this, ignore some bit fields. See Patchset 1 | 86b3146261: https://review.coreboot.org/c/coreboot/+/43410/1
[1] https://github.com/maxpoliak/pch-pads-parser [2] https://review.coreboot.org/c/coreboot/+/35643
Change-Id: I18c0c321561eee04ff927681b0a231f6d79c63e2 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/mainboard/51nb/x210/gpio.h 1 file changed, 164 insertions(+), 164 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/43410/5
Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43410 )
Change subject: mb/51nb/x210/gpio: Convert configuration to macros ......................................................................
Patch Set 5:
(1 comment)
Patch Set 3:
thinking out loud: would it make more sense to drop the invalid config bits from the raw values first, then convert the "corrected" raw values to macros cleanly?
Ok, I'll do it later.
https://review.coreboot.org/c/coreboot/+/43410/5/src/mainboard/51nb/x210/gpi... File src/mainboard/51nb/x210/gpio.h:
https://review.coreboot.org/c/coreboot/+/43410/5/src/mainboard/51nb/x210/gpi... PS5, Line 131: PAD_CFG_GPIO_BIDIRECT What do you think about this? CB:42914
Hello build bot (Jenkins), Nico Huber, Matt DeVillier, Paul Menzel, Angel Pons, Michael Niewöhner,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43410
to look at the new patch set (#6).
Change subject: mb/51nb/x210/gpio: 4/4 Convert field macros to PAD_CFG ......................................................................
mb/51nb/x210/gpio: 4/4 Convert field macros to PAD_CFG
Converts bit field macros to target PAD_CFG_*() macros. To do this, the following command was used:
./intelp2m -n -t 1 -file ../../coreboot/src/mainboard/51nb/x210/gpio.h
This is part of the patch set "mb/51nb/x210/gpio: Rewrite pad config using intelp2m":
- 1/4 Decode raw register values - 2/4 Exclude fields for PAD_CFG - 3/4 Fixes PAD_RESET to convert to PAD_NC() - 4/4 Convert field macros to PAD_CFG
[*] The test with BUILD_TIMELESS = 1 is successfully. The images before and after the patch are the same.
Change-Id: I18c0c321561eee04ff927681b0a231f6d79c63e2 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/mainboard/51nb/x210/gpio.h 1 file changed, 162 insertions(+), 162 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/43410/6
Hello build bot (Jenkins), Nico Huber, Matt DeVillier, Paul Menzel, Angel Pons, Michael Niewöhner,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43410
to look at the new patch set (#7).
Change subject: mb/51nb/x210/gpio: 4/4 Convert field macros to PAD_CFG ......................................................................
mb/51nb/x210/gpio: 4/4 Convert field macros to PAD_CFG
Converts bit field macros to target PAD_CFG_*() macros. To do this, the following command was used:
./intelp2m -n -t 1 -file ../../coreboot/src/mainboard/51nb/x210/gpio.h
This is part of the patch set "mb/51nb/x210/gpio: Rewrite pad config using intelp2m":
CB:43566 - 1/4 Decode raw register values CB:43567 - 2/4 Exclude fields for PAD_CFG CB:43568 - 3/4 Fixes PAD_RESET to convert to PAD_NC() CB:43410 - 4/4 Convert field macros to PAD_CFG
[*] The test with BUILD_TIMELESS = 1 is successfully. The images before and after the patch are the same.
Change-Id: I18c0c321561eee04ff927681b0a231f6d79c63e2 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/mainboard/51nb/x210/gpio.h 1 file changed, 162 insertions(+), 162 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/43410/7
Hello build bot (Jenkins), Nico Huber, Matt DeVillier, Paul Menzel, Angel Pons, Michael Niewöhner,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43410
to look at the new patch set (#8).
Change subject: mb/51nb/x210/gpio: 4/4 Convert field macros to PAD_CFG ......................................................................
mb/51nb/x210/gpio: 4/4 Convert field macros to PAD_CFG
Converts bit field macros to target PAD_CFG_*() macros. To do this, the following command was used:
./intelp2m -n -t 1 -file ../../coreboot/src/mainboard/51nb/x210/gpio.h
This is part of the patch set "mb/51nb/x210/gpio: Rewrite pad config using intelp2m":
CB:43566 - 1/4 Decode raw register values CB:43567 - 2/4 Exclude fields for PAD_CFG CB:43568 - 3/4 Fixes PAD_RESET to convert to PAD_NC() CB:43410 - 4/4 Convert field macros to PAD_CFG
Tested with BUILD_TIMELESS=1, 51NB-X210, remains identical.
Change-Id: I18c0c321561eee04ff927681b0a231f6d79c63e2 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/mainboard/51nb/x210/gpio.h 1 file changed, 162 insertions(+), 162 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/43410/8
Hello build bot (Jenkins), Nico Huber, Matt DeVillier, Paul Menzel, Angel Pons, Michael Niewöhner,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43410
to look at the new patch set (#9).
Change subject: mb/51nb/x210/gpio: 4/4 Convert field macros to PAD_CFG ......................................................................
mb/51nb/x210/gpio: 4/4 Convert field macros to PAD_CFG
Converts bit field macros to target PAD_CFG_*() macros. To do this, the following command was used:
./intelp2m -n -t 1 -file ../../coreboot/src/mainboard/51nb/x210/gpio.h
This is part of the patch set "mb/51nb/x210/gpio: Rewrite pad config using intelp2m":
CB:43566 - 1/4 Decode raw register values CB:43567 - 2/4 Exclude fields for PAD_CFG CB:43568 - 3/4 Fixes PAD_RESET to convert to PAD_NC() CB:43410 - 4/4 Convert field macros to PAD_CFG
Tested with BUILD_TIMELESS=1, 51NB-X210, remains identical.
Change-Id: I18c0c321561eee04ff927681b0a231f6d79c63e2 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/mainboard/51nb/x210/gpio.h 1 file changed, 162 insertions(+), 162 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/43410/9
Hello build bot (Jenkins), Nico Huber, Matt DeVillier, Paul Menzel, Angel Pons, Michael Niewöhner,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43410
to look at the new patch set (#10).
Change subject: mb/51nb/x210/gpio: 4/4 Convert field macros to PAD_CFG ......................................................................
mb/51nb/x210/gpio: 4/4 Convert field macros to PAD_CFG
Converts bit fields macros to target PAD_CFG_*() macros. To do this, the following command was used:
./intelp2m -n -t 1 -file ../../src/mainboard/51nb/x210/gpio.h
This is part of the patch set "mb/51nb/x210/gpio: Rewrite pad config using intelp2m":
CB:43566 - 1/4 Decode raw register values CB:43567 - 2/4 Exclude fields for PAD_CFG CB:43568 - 3/4 Fixes PAD_RESET to convert to PAD_NC() CB:43410 - 4/4 Convert field macros to PAD_CFG
Tested with BUILD_TIMELESS=1, 51NB-X210, remains identical.
Change-Id: I18c0c321561eee04ff927681b0a231f6d79c63e2 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/mainboard/51nb/x210/gpio.h 1 file changed, 162 insertions(+), 162 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/43410/10
Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43410 )
Change subject: mb/51nb/x210/gpio: 4/4 Convert field macros to PAD_CFG ......................................................................
Patch Set 10:
Patch Set 5:
(1 comment)
Patch Set 3:
thinking out loud: would it make more sense to drop the invalid config bits from the raw values first, then convert the "corrected" raw values to macros cleanly?
Ok, I'll do it later.
Done CB:43566 - 1/4 Decode raw register values CB:43567 - 2/4 Exclude fields for PAD_CFG CB:43568 - 3/4 Fixes PAD_RESET to convert to PAD_NC() CB:43410 - 4/4 Convert field macros to PAD_CFG
Hello build bot (Jenkins), Nico Huber, Matt DeVillier, Paul Menzel, Angel Pons, Michael Niewöhner,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43410
to look at the new patch set (#11).
Change subject: mb/51nb/x210/gpio: 4/4 Convert field macros to PAD_CFG ......................................................................
mb/51nb/x210/gpio: 4/4 Convert field macros to PAD_CFG
Converts bit fields macros to target PAD_CFG_*() macros. To do this, the following command was used:
./intelp2m -n -t 1 -file ../../src/mainboard/51nb/x210/gpio.h
This is part of the patch set "mb/51nb/x210/gpio: Rewrite pad config using intelp2m":
CB:43566 - 1/4 Decode raw register values CB:43567 - 2/4 Exclude fields for PAD_CFG CB:43568 - 3/4 Fixes PAD_RESET to convert to PAD_NC() CB:43410 - 4/4 Convert field macros to PAD_CFG
Tested with BUILD_TIMELESS=1, 51NB-X210, remains identical.
Change-Id: I18c0c321561eee04ff927681b0a231f6d79c63e2 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/mainboard/51nb/x210/gpio.h 1 file changed, 162 insertions(+), 162 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/43410/11
Hello build bot (Jenkins), Nico Huber, Matt DeVillier, Paul Menzel, Angel Pons, Michael Niewöhner,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43410
to look at the new patch set (#13).
Change subject: mb/51nb/x210/gpio: 4/4 Convert field macros to PAD_CFG ......................................................................
mb/51nb/x210/gpio: 4/4 Convert field macros to PAD_CFG
Converts bit fields macros to target PAD_CFG_*() macros. To do this, the following command was used:
./intelp2m -n -t 1 -file ../../src/mainboard/51nb/x210/gpio.h
This is part of the patch set "mb/51nb/x210/gpio: Rewrite pad config using intelp2m":
CB:43566 - 1/4 Decode raw register values CB:43567 - 2/4 Exclude fields for PAD_CFG CB:43568 - 3/4 Fixes PAD_RESET to convert to PAD_NC() CB:43410 - 4/4 Convert field macros to PAD_CFG
Tested with BUILD_TIMELESS=1, 51NB-X210, remains identical.
Change-Id: I18c0c321561eee04ff927681b0a231f6d79c63e2 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/mainboard/51nb/x210/gpio.h 1 file changed, 174 insertions(+), 162 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/43410/13
Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43410 )
Change subject: mb/51nb/x210/gpio: 4/4 Convert field macros to PAD_CFG ......................................................................
Patch Set 13:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43410/5/src/mainboard/51nb/x210/gpi... File src/mainboard/51nb/x210/gpio.h:
https://review.coreboot.org/c/coreboot/+/43410/5/src/mainboard/51nb/x210/gpi... PS5, Line 131: PAD_CFG_GPIO_BIDIRECT
What do you think about this? CB:42914
added to gpio.h in the latest patch
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43410 )
Change subject: mb/51nb/x210/gpio: 4/4 Convert field macros to PAD_CFG ......................................................................
Patch Set 13:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43410/13/src/mainboard/51nb/x210/gp... File src/mainboard/51nb/x210/gpio.h:
https://review.coreboot.org/c/coreboot/+/43410/13/src/mainboard/51nb/x210/gp... PS13, Line 150: SLP_S4 since there are no schematics, like for the X11 series, let's get rid of the comments?
Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43410 )
Change subject: mb/51nb/x210/gpio: 4/4 Convert field macros to PAD_CFG ......................................................................
Patch Set 14:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43410/13/src/mainboard/51nb/x210/gp... File src/mainboard/51nb/x210/gpio.h:
https://review.coreboot.org/c/coreboot/+/43410/13/src/mainboard/51nb/x210/gp... PS13, Line 150: SLP_S4
since there are no schematics, like for the X11 series, let's get rid of the comments?
Done in https://review.coreboot.org/c/coreboot/+/45371
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43410 )
Change subject: mb/51nb/x210/gpio: 4/4 Convert field macros to PAD_CFG ......................................................................
Patch Set 14: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/43410/14/src/mainboard/51nb/x210/gp... File src/mainboard/51nb/x210/gpio.h:
https://review.coreboot.org/c/coreboot/+/43410/14/src/mainboard/51nb/x210/gp... PS14, Line 9: /* : * Bidirectional GPIO port when both RX and TX buffer is enabled : * TODO: move this macros to src/soc/intel/common/block/include/intelblocks/gpio_defs.h : */ : #ifndef PAD_CFG_GPIO_BIDIRECT : #define PAD_CFG_GPIO_BIDIRECT(pad, val, pull, rst, trig, own) \ : _PAD_CFG_STRUCT(pad, \ : PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_TRIG(trig) | \ : PAD_BUF(NO_DISABLE) | val, \ : PAD_PULL(pull) | PAD_CFG_OWN_GPIO(own)) : #endif : todo
Hello build bot (Jenkins), Nico Huber, Matt DeVillier, Paul Menzel, Angel Pons, Michael Niewöhner,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43410
to look at the new patch set (#15).
Change subject: mb/51nb/x210/gpio: 4/4 Convert field macros to PAD_CFG ......................................................................
mb/51nb/x210/gpio: 4/4 Convert field macros to PAD_CFG
Converts bit fields macros to target PAD_CFG_*() macros. To do this, the following command was used:
./intelp2m -n -t 1 -file ../../src/mainboard/51nb/x210/gpio.h
This is part of the patch set "mb/51nb/x210/gpio: Rewrite pad config using intelp2m":
CB:43566 - 1/4 Decode raw register values CB:43567 - 2/4 Exclude fields for PAD_CFG CB:43568 - 3/4 Fixes PAD_RESET to convert to PAD_NC() CB:43410 - 4/4 Convert field macros to PAD_CFG
Tested with BUILD_TIMELESS=1, 51NB-X210, remains identical.
Change-Id: I18c0c321561eee04ff927681b0a231f6d79c63e2 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/mainboard/51nb/x210/gpio.h 1 file changed, 174 insertions(+), 162 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/43410/15
Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43410 )
Change subject: mb/51nb/x210/gpio: 4/4 Convert field macros to PAD_CFG ......................................................................
Patch Set 15:
(1 comment)
https://review.coreboot.org/c/coreboot/+/43410/14/src/mainboard/51nb/x210/gp... File src/mainboard/51nb/x210/gpio.h:
https://review.coreboot.org/c/coreboot/+/43410/14/src/mainboard/51nb/x210/gp... PS14, Line 9: /* : * Bidirectional GPIO port when both RX and TX buffer is enabled : * TODO: move this macros to src/soc/intel/common/block/include/intelblocks/gpio_defs.h : */ : #ifndef PAD_CFG_GPIO_BIDIRECT : #define PAD_CFG_GPIO_BIDIRECT(pad, val, pull, rst, trig, own) \ : _PAD_CFG_STRUCT(pad, \ : PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_TRIG(trig) | \ : PAD_BUF(NO_DISABLE) | val, \ : PAD_PULL(pull) | PAD_CFG_OWN_GPIO(own)) : #endif :
todo
Done
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43410 )
Change subject: mb/51nb/x210/gpio: 4/4 Convert field macros to PAD_CFG ......................................................................
Patch Set 15: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/43410 )
Change subject: mb/51nb/x210/gpio: 4/4 Convert field macros to PAD_CFG ......................................................................
mb/51nb/x210/gpio: 4/4 Convert field macros to PAD_CFG
Converts bit fields macros to target PAD_CFG_*() macros. To do this, the following command was used:
./intelp2m -n -t 1 -file ../../src/mainboard/51nb/x210/gpio.h
This is part of the patch set "mb/51nb/x210/gpio: Rewrite pad config using intelp2m":
CB:43566 - 1/4 Decode raw register values CB:43567 - 2/4 Exclude fields for PAD_CFG CB:43568 - 3/4 Fixes PAD_RESET to convert to PAD_NC() CB:43410 - 4/4 Convert field macros to PAD_CFG
Tested with BUILD_TIMELESS=1, 51NB-X210, remains identical.
Change-Id: I18c0c321561eee04ff927681b0a231f6d79c63e2 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/43410 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/51nb/x210/gpio.h 1 file changed, 174 insertions(+), 162 deletions(-)
Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved
diff --git a/src/mainboard/51nb/x210/gpio.h b/src/mainboard/51nb/x210/gpio.h index 533cf5a..f6d6519 100644 --- a/src/mainboard/51nb/x210/gpio.h +++ b/src/mainboard/51nb/x210/gpio.h @@ -6,174 +6,186 @@ #include <soc/gpe.h> #include <soc/gpio.h>
+/* + * Bidirectional GPIO port when both RX and TX buffer is enabled + * todo: move this macros to src/soc/intel/common/block/include/intelblocks/gpio_defs.h + */ +#ifndef PAD_CFG_GPIO_BIDIRECT +#define PAD_CFG_GPIO_BIDIRECT(pad, val, pull, rst, trig, own) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_TRIG(trig) | \ + PAD_BUF(NO_DISABLE) | val, \ + PAD_PULL(pull) | PAD_CFG_OWN_GPIO(own)) +#endif + #ifndef __ACPI__
/* Pad configuration in ramstage. */ static const struct pad_config gpio_table[] = { -/* RCIN# */_PAD_CFG_STRUCT(GPP_A0, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* LAD0 */_PAD_CFG_STRUCT(GPP_A1, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(NATIVE)), -/* LAD1 */_PAD_CFG_STRUCT(GPP_A2, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(NATIVE)), -/* LAD2 */_PAD_CFG_STRUCT(GPP_A3, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(NATIVE)), -/* LAD3 */_PAD_CFG_STRUCT(GPP_A4, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(NATIVE)), -/* LFRAME# */_PAD_CFG_STRUCT(GPP_A5, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* SERIRQ */_PAD_CFG_STRUCT(GPP_A6, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* GPIO */_PAD_CFG_STRUCT(GPP_A7, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), -/* GPIO */_PAD_CFG_STRUCT(GPP_A8, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(20K_PU)), -/* CLKOUT_LPC0 */_PAD_CFG_STRUCT(GPP_A9, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(20K_PD)), -/* CLKOUT_LPC1 */_PAD_CFG_STRUCT(GPP_A10, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(20K_PD)), -/* GPIO */_PAD_CFG_STRUCT(GPP_A11, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), -/* GPIO */_PAD_CFG_STRUCT(GPP_A12, PAD_FUNC(GPIO) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), -/* SUSWARN#/SUSPWRDNACK */_PAD_CFG_STRUCT(GPP_A13, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* SUS_STAT# */_PAD_CFG_STRUCT(GPP_A14, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* SUS_ACK# */_PAD_CFG_STRUCT(GPP_A15, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(20K_PU)), -/* CLKOUT_48 */_PAD_CFG_STRUCT(GPP_A16, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* ISH_GP7 */_PAD_CFG_STRUCT(GPP_A17, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* GPIO */_PAD_CFG_STRUCT(GPP_A18, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), -/* GPIO */_PAD_CFG_STRUCT(GPP_A19, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), -/* GPIO */_PAD_CFG_STRUCT(GPP_A20, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), -/* GPIO */_PAD_CFG_STRUCT(GPP_A21, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), -/* GPIO */_PAD_CFG_STRUCT(GPP_A22, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), -/* GPIO */_PAD_CFG_STRUCT(GPP_A23, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), PAD_PULL(20K_PD)), -/* n/a */_PAD_CFG_STRUCT(GPP_B0, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* n/a */_PAD_CFG_STRUCT(GPP_B1, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* GPIO */_PAD_CFG_STRUCT(GPP_B2, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), -/* GPIO */_PAD_CFG_STRUCT(GPP_B3, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), -/* GPIO */_PAD_CFG_STRUCT(GPP_B4, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, 0), -/* SRCCLKREQ0# */_PAD_CFG_STRUCT(GPP_B5, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* SRCCLKREQ1# */_PAD_CFG_STRUCT(GPP_B6, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* SRCCLKREQ2# */_PAD_CFG_STRUCT(GPP_B7, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* SRCCLKREQ3# */_PAD_CFG_STRUCT(GPP_B8, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* SRCCLKREQ4# */_PAD_CFG_STRUCT(GPP_B9, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* GPIO */_PAD_CFG_STRUCT(GPP_B10, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), -/* n/a */_PAD_CFG_STRUCT(GPP_B11, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* SLP_S0# */_PAD_CFG_STRUCT(GPP_B12, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* PLTRST# */_PAD_CFG_STRUCT(GPP_B13, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* GPIO */_PAD_CFG_STRUCT(GPP_B14, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, PAD_PULL(20K_PD)), -/* GPIO */_PAD_CFG_STRUCT(GPP_B15, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), -/* GPIO */_PAD_CFG_STRUCT(GPP_B16, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), -/* GPIO */_PAD_CFG_STRUCT(GPP_B17, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), PAD_PULL(20K_PU)), -/* GPIO */_PAD_CFG_STRUCT(GPP_B18, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), PAD_PULL(20K_PU)), -/* GPIO */_PAD_CFG_STRUCT(GPP_B19, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), -/* GSPI1_CLK */_PAD_CFG_STRUCT(GPP_B20, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(20K_PD)), -/* GSPI1_MISO */_PAD_CFG_STRUCT(GPP_B21, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(20K_PD)), -/* GSPIO_MOSI */_PAD_CFG_STRUCT(GPP_B22, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(20K_PD)), -/* GPIO */_PAD_CFG_STRUCT(GPP_B23, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, PAD_PULL(20K_PD)), -/* SMBCLK */_PAD_CFG_STRUCT(GPP_C0, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* SMBDATA */_PAD_CFG_STRUCT(GPP_C1, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(20K_PD)), -/* GPIO */_PAD_CFG_STRUCT(GPP_C2, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, PAD_PULL(20K_PD)), -/* SML0CLK */_PAD_CFG_STRUCT(GPP_C3, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(20K_PU)), -/* SML0DATA */_PAD_CFG_STRUCT(GPP_C4, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(20K_PU)), -/* GPIO */_PAD_CFG_STRUCT(GPP_C5, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), PAD_PULL(20K_PD)), +/* RCIN# */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), +/* LAD0 */ PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1), +/* LAD1 */ PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1), +/* LAD2 */ PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1), +/* LAD3 */ PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1), +/* LFRAME# */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), +/* SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), +/* GPIO */ PAD_CFG_GPO(GPP_A7, 1, DEEP), +/* GPIO */ PAD_NC(GPP_A8, 20K_PU), +/* CLKOUT_LPC0 */ PAD_CFG_NF(GPP_A9, 20K_PD, DEEP, NF1), +/* CLKOUT_LPC1 */ PAD_CFG_NF(GPP_A10, 20K_PD, DEEP, NF1), +/* GPIO */ PAD_CFG_GPO(GPP_A11, 0, DEEP), +/* GPIO */ PAD_CFG_GPO(GPP_A12, 0, PWROK), +/* SUSWARN#/SUSPWRDNACK */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), +/* SUS_STAT# */ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), +/* SUS_ACK# */ PAD_CFG_NF(GPP_A15, 20K_PU, DEEP, NF1), +/* CLKOUT_48 */ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), +/* ISH_GP7 */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1), +/* GPIO */ PAD_NC(GPP_A18, NONE), +/* GPIO */ PAD_NC(GPP_A19, NONE), +/* GPIO */ PAD_NC(GPP_A20, NONE), +/* GPIO */ PAD_NC(GPP_A21, NONE), +/* GPIO */ PAD_CFG_GPO(GPP_A22, 1, DEEP), +/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_A23, 20K_PD, DEEP, OFF, ACPI), +/* n/a */ PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), +/* n/a */ PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), +/* GPIO */ PAD_NC(GPP_B2, NONE), +/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_B3, NONE, PLTRST, OFF, ACPI), +/* GPIO */ PAD_CFG_GPO(GPP_B4, 1, DEEP), +/* SRCCLKREQ0# */ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), +/* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), +/* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), +/* SRCCLKREQ3# */ PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), +/* SRCCLKREQ4# */ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), +/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_B10, NONE, DEEP, OFF, ACPI), +/* n/a */ PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), +/* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), +/* PLTRST# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), +/* GPIO */ PAD_CFG_TERM_GPO(GPP_B14, 1, 20K_PD, DEEP), +/* GPIO */ PAD_NC(GPP_B15, NONE), +/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_B16, NONE, PLTRST, OFF, ACPI), +/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_B17, 20K_PU, PLTRST, OFF, ACPI), +/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_B18, 20K_PU, PLTRST, OFF, ACPI), +/* GPIO */ PAD_NC(GPP_B19, NONE), +/* GSPI1_CLK */ PAD_CFG_NF(GPP_B20, 20K_PD, DEEP, NF1), +/* GSPI1_MISO */ PAD_CFG_NF(GPP_B21, 20K_PD, DEEP, NF1), +/* GSPIO_MOSI */ PAD_CFG_NF(GPP_B22, 20K_PD, DEEP, NF1), +/* GPIO */ PAD_CFG_TERM_GPO(GPP_B23, 1, 20K_PD, DEEP), +/* SMBCLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), +/* SMBDATA */ PAD_CFG_NF(GPP_C1, 20K_PD, DEEP, NF1), +/* GPIO */ PAD_CFG_TERM_GPO(GPP_C2, 1, 20K_PD, DEEP), +/* SML0CLK */ PAD_CFG_NF(GPP_C3, 20K_PU, DEEP, NF1), +/* SML0DATA */ PAD_CFG_NF(GPP_C4, 20K_PU, DEEP, NF1), +/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_C5, 20K_PD, DEEP, OFF, ACPI), /* RESERVED - GPP_C6 */ /* RESERVED - GPP_C7 */ -/* UART0_RXD */_PAD_CFG_STRUCT(GPP_C8, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(20K_PU)), -/* UART0_TXD */_PAD_CFG_STRUCT(GPP_C9, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* UART0_RTS# */_PAD_CFG_STRUCT(GPP_C10, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* UART0_CTS# */_PAD_CFG_STRUCT(GPP_C11, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* UART1_RXD */_PAD_CFG_STRUCT(GPP_C12, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* UART1_TXD */_PAD_CFG_STRUCT(GPP_C13, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* UART1_RTS# */_PAD_CFG_STRUCT(GPP_C14, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* UART1_CTS# */_PAD_CFG_STRUCT(GPP_C15, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* I2C0_SDA */_PAD_CFG_STRUCT(GPP_C16, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(20K_PU)), -/* I2C0_SCL */_PAD_CFG_STRUCT(GPP_C17, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(20K_PU)), -/* I2C1_SDA */_PAD_CFG_STRUCT(GPP_C18, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(20K_PU)), -/* I2C1_SCL */_PAD_CFG_STRUCT(GPP_C19, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(20K_PU)), -/* UART2_RXD */_PAD_CFG_STRUCT(GPP_C20, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(20K_PU)), -/* UART2_TXD */_PAD_CFG_STRUCT(GPP_C21, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* UART2_RTS# */_PAD_CFG_STRUCT(GPP_C22, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* UART2_CTS# */_PAD_CFG_STRUCT(GPP_C23, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* n/a */_PAD_CFG_STRUCT(GPP_D0, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* n/a */_PAD_CFG_STRUCT(GPP_D1, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* n/a */_PAD_CFG_STRUCT(GPP_D2, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* n/a */_PAD_CFG_STRUCT(GPP_D3, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* ISH_I2C2_SDA */_PAD_CFG_STRUCT(GPP_D4, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* I2S_SFRM */_PAD_CFG_STRUCT(GPP_D5, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(20K_PU)), -/* I2S_TXD */_PAD_CFG_STRUCT(GPP_D6, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(20K_PU)), -/* I2S_RXD */_PAD_CFG_STRUCT(GPP_D7, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(20K_PU)), -/* I2S_SCLK */_PAD_CFG_STRUCT(GPP_D8, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(20K_PU)), -/* GPIO */_PAD_CFG_STRUCT(GPP_D9, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), PAD_PULL(20K_PU)), -/* GPIO */_PAD_CFG_STRUCT(GPP_D10, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), PAD_PULL(20K_PU)), -/* GPIO */_PAD_CFG_STRUCT(GPP_D11, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), PAD_PULL(20K_PU)), -/* GPIO */_PAD_CFG_STRUCT(GPP_D12, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), PAD_PULL(20K_PU)), -/* ISH_UART0_RXD */_PAD_CFG_STRUCT(GPP_D13, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(20K_PU)), -/* ISH_UART0_TXD */_PAD_CFG_STRUCT(GPP_D14, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(20K_PU)), -/* ISH_UART0_RTS# */_PAD_CFG_STRUCT(GPP_D15, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* ISH_UART0_CTS# */_PAD_CFG_STRUCT(GPP_D16, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* DMIC_CLK1 */_PAD_CFG_STRUCT(GPP_D17, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* DMIC_DATA1 */_PAD_CFG_STRUCT(GPP_D18, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(20K_PD)), -/* DMIC_CLK0 */_PAD_CFG_STRUCT(GPP_D19, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* DMIC_DATA0 */_PAD_CFG_STRUCT(GPP_D20, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(20K_PD)), -/* n/a */_PAD_CFG_STRUCT(GPP_D21, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* n/a */_PAD_CFG_STRUCT(GPP_D22, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* ISH_I2C2_SCL */_PAD_CFG_STRUCT(GPP_D23, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* GPIO */_PAD_CFG_STRUCT(GPP_E0, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), -/* GPIO */_PAD_CFG_STRUCT(GPP_E1, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), -/* GPIO */_PAD_CFG_STRUCT(GPP_E2, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), -/* GPIO */_PAD_CFG_STRUCT(GPP_E3, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), -/* GPIO */_PAD_CFG_STRUCT(GPP_E4, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), -/* SATA_DEVSLP1 */_PAD_CFG_STRUCT(GPP_E5, PAD_FUNC(NF1), 0), -/* SATA_DEVSLP2 */_PAD_CFG_STRUCT(GPP_E6, PAD_FUNC(NF1), 0), -/* GPIO */_PAD_CFG_STRUCT(GPP_E7, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), -/* SATA_LED# */_PAD_CFG_STRUCT(GPP_E8, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* USB_OC0# */_PAD_CFG_STRUCT(GPP_E9, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* USB_OC1# */_PAD_CFG_STRUCT(GPP_E10, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* USB_OC2# */_PAD_CFG_STRUCT(GPP_E11, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* GPIO */_PAD_CFG_STRUCT(GPP_E12, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), -/* n/a */_PAD_CFG_STRUCT(GPP_E13, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* n/a */_PAD_CFG_STRUCT(GPP_E14, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* GPIO */_PAD_CFG_STRUCT(GPP_E15, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_IRQ_ROUTE(SCI) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE), 0), -/* GPIO */_PAD_CFG_STRUCT(GPP_E16, PAD_FUNC(GPIO) | PAD_RESET(PLTRST) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), -/* n/a */_PAD_CFG_STRUCT(GPP_E17, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* n/a */_PAD_CFG_STRUCT(GPP_E18, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(20K_PU)), -/* n/a */_PAD_CFG_STRUCT(GPP_E19, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(20K_PD)), -/* n/a */_PAD_CFG_STRUCT(GPP_E20, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(20K_PU)), -/* n/a */_PAD_CFG_STRUCT(GPP_E21, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(20K_PD)), -/* GPIO */_PAD_CFG_STRUCT(GPP_E22, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF), 0), -/* GPIO */_PAD_CFG_STRUCT(GPP_E23, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | 1, PAD_PULL(20K_PD)), -/* BATLOW# */_PAD_CFG_STRUCT(GPD0, PAD_FUNC(NF1), PAD_PULL(20K_PU)), -/* ACPRESENT */_PAD_CFG_STRUCT(GPD1, PAD_FUNC(NF1), 0), -/* LAN_WAKE# */_PAD_CFG_STRUCT(GPD2, PAD_FUNC(NF1), PAD_PULL(NATIVE)), -/* PWRBTN# */_PAD_CFG_STRUCT(GPD3, PAD_FUNC(NF1), PAD_PULL(20K_PU)), -/* SLP_S3# */_PAD_CFG_STRUCT(GPD4, PAD_FUNC(NF1), 0), -/* SLP_S4# */_PAD_CFG_STRUCT(GPD5, PAD_FUNC(NF1), 0), -/* SLP_A# */_PAD_CFG_STRUCT(GPD6, PAD_FUNC(NF1), 0), -/* GPIO */_PAD_CFG_STRUCT(GPD7, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), -/* SUSCLK */_PAD_CFG_STRUCT(GPD8, PAD_FUNC(NF1), 0), -/* SLP_WLAN# */_PAD_CFG_STRUCT(GPD9, PAD_FUNC(NF1), 0), -/* SLP_S5# */_PAD_CFG_STRUCT(GPD10, PAD_FUNC(NF1), 0), -/* LANPHYPC */_PAD_CFG_STRUCT(GPD11, PAD_FUNC(NF1), 0), -/* SATAXPCIE3 */_PAD_CFG_STRUCT(GPP_F0, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* SATAXPCIE4 */_PAD_CFG_STRUCT(GPP_F1, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* SATAXPCIE5 */_PAD_CFG_STRUCT(GPP_F2, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* SATAXPCIE6 */_PAD_CFG_STRUCT(GPP_F3, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* SATAXPCIE7 */_PAD_CFG_STRUCT(GPP_F4, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_CFG1_TOL_1V8 | PAD_PULL(20K_PU)), -/* SATA_DEVSLP3 */_PAD_CFG_STRUCT(GPP_F5, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_CFG1_TOL_1V8 | PAD_PULL(20K_PU)), -/* SATA_DEVSLP4 */_PAD_CFG_STRUCT(GPP_F6, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_CFG1_TOL_1V8 | PAD_PULL(20K_PU)), -/* SATA_DEVSLP5 */_PAD_CFG_STRUCT(GPP_F7, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_CFG1_TOL_1V8 | PAD_PULL(20K_PU)), -/* SATA_DEVSLP6 */_PAD_CFG_STRUCT(GPP_F8, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_CFG1_TOL_1V8 | PAD_PULL(20K_PU)), -/* SATA_DEVSLP7 */_PAD_CFG_STRUCT(GPP_F9, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_CFG1_TOL_1V8 | PAD_PULL(20K_PU)), -/* n/a */_PAD_CFG_STRUCT(GPP_F10, PAD_FUNC(NF2) | PAD_RESET(DEEP), PAD_CFG1_TOL_1V8 | PAD_PULL(20K_PU)), -/* n/a */_PAD_CFG_STRUCT(GPP_F11, PAD_FUNC(NF2) | PAD_RESET(DEEP), PAD_CFG1_TOL_1V8 | PAD_PULL(20K_PU)), -/* SATA_SDATAOUT1 */_PAD_CFG_STRUCT(GPP_F12, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* SATA_SDATAOUT2 */_PAD_CFG_STRUCT(GPP_F13, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* n/a */_PAD_CFG_STRUCT(GPP_F14, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* USB_OC4# */_PAD_CFG_STRUCT(GPP_F15, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* USB_OC5# */_PAD_CFG_STRUCT(GPP_F16, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* USB_OC6# */_PAD_CFG_STRUCT(GPP_F17, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* USB_OC7# */_PAD_CFG_STRUCT(GPP_F18, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* eDP_VDDEN */_PAD_CFG_STRUCT(GPP_F19, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* eDP_BKLTEN */_PAD_CFG_STRUCT(GPP_F20, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* eDP_BKLTCTL */_PAD_CFG_STRUCT(GPP_F21, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* n/a */_PAD_CFG_STRUCT(GPP_F22, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* GPIO */_PAD_CFG_STRUCT(GPP_F23, PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), 0), -/* FAN_TACH_0 */_PAD_CFG_STRUCT(GPP_G0, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* FAN_TACH_1 */_PAD_CFG_STRUCT(GPP_G1, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* FAN_TACH_2 */_PAD_CFG_STRUCT(GPP_G2, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* FAN_TACH_3 */_PAD_CFG_STRUCT(GPP_G3, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* FAN_TACH_4 */_PAD_CFG_STRUCT(GPP_G4, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* FAN_TACH_5 */_PAD_CFG_STRUCT(GPP_G5, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* FAN_TACH_6 */_PAD_CFG_STRUCT(GPP_G6, PAD_FUNC(NF1) | PAD_RESET(DEEP), 0), -/* FAN_TACH_7 */_PAD_CFG_STRUCT(GPP_G7, PAD_FUNC(NF1) | PAD_RESET(DEEP), PAD_PULL(20K_PD)), +/* UART0_RXD */ PAD_CFG_NF(GPP_C8, 20K_PU, DEEP, NF1), +/* UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), +/* UART0_RTS# */ PAD_CFG_NF(GPP_C10, NONE, DEEP, NF1), +/* UART0_CTS# */ PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1), +/* UART1_RXD */ PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), +/* UART1_TXD */ PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), +/* UART1_RTS# */ PAD_CFG_NF(GPP_C14, NONE, DEEP, NF1), +/* UART1_CTS# */ PAD_CFG_NF(GPP_C15, NONE, DEEP, NF1), +/* I2C0_SDA */ PAD_CFG_NF(GPP_C16, 20K_PU, DEEP, NF1), +/* I2C0_SCL */ PAD_CFG_NF(GPP_C17, 20K_PU, DEEP, NF1), +/* I2C1_SDA */ PAD_CFG_NF(GPP_C18, 20K_PU, DEEP, NF1), +/* I2C1_SCL */ PAD_CFG_NF(GPP_C19, 20K_PU, DEEP, NF1), +/* UART2_RXD */ PAD_CFG_NF(GPP_C20, 20K_PU, DEEP, NF1), +/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), +/* UART2_RTS# */ PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1), +/* UART2_CTS# */ PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1), +/* n/a */ PAD_CFG_NF(GPP_D0, NONE, DEEP, NF1), +/* n/a */ PAD_CFG_NF(GPP_D1, NONE, DEEP, NF1), +/* n/a */ PAD_CFG_NF(GPP_D2, NONE, DEEP, NF1), +/* n/a */ PAD_CFG_NF(GPP_D3, NONE, DEEP, NF1), +/* ISH_I2C2_SDA */ PAD_CFG_NF(GPP_D4, NONE, DEEP, NF1), +/* I2S_SFRM */ PAD_CFG_NF(GPP_D5, 20K_PU, DEEP, NF1), +/* I2S_TXD */ PAD_CFG_NF(GPP_D6, 20K_PU, DEEP, NF1), +/* I2S_RXD */ PAD_CFG_NF(GPP_D7, 20K_PU, DEEP, NF1), +/* I2S_SCLK */ PAD_CFG_NF(GPP_D8, 20K_PU, DEEP, NF1), +/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_D9, 20K_PU, DEEP, OFF, ACPI), +/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_D10, 20K_PU, DEEP, OFF, ACPI), +/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_D11, 20K_PU, DEEP, OFF, ACPI), +/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_D12, 20K_PU, DEEP, OFF, ACPI), +/* ISH_UART0_RXD */ PAD_CFG_NF(GPP_D13, 20K_PU, DEEP, NF1), +/* ISH_UART0_TXD */ PAD_CFG_NF(GPP_D14, 20K_PU, DEEP, NF1), +/* ISH_UART0_RTS# */ PAD_CFG_NF(GPP_D15, NONE, DEEP, NF1), +/* ISH_UART0_CTS# */ PAD_CFG_NF(GPP_D16, NONE, DEEP, NF1), +/* DMIC_CLK1 */ PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), +/* DMIC_DATA1 */ PAD_CFG_NF(GPP_D18, 20K_PD, DEEP, NF1), +/* DMIC_CLK0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), +/* DMIC_DATA0 */ PAD_CFG_NF(GPP_D20, 20K_PD, DEEP, NF1), +/* n/a */ PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1), +/* n/a */ PAD_CFG_NF(GPP_D22, NONE, DEEP, NF1), +/* ISH_I2C2_SCL */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), +/* GPIO */ PAD_CFG_GPO(GPP_E0, 0, DEEP), +/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_E1, NONE, DEEP, OFF, ACPI), +/* GPIO */ PAD_NC(GPP_E2, NONE), +/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_E3, NONE, DEEP, OFF, ACPI), +/* GPIO */ PAD_NC(GPP_E4, NONE), +/* SATA_DEVSLP1 */ PAD_CFG_NF(GPP_E5, NONE, PWROK, NF1), +/* SATA_DEVSLP2 */ PAD_CFG_NF(GPP_E6, NONE, PWROK, NF1), +/* GPIO */ PAD_NC(GPP_E7, NONE), +/* SATA_LED# */ PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), +/* USB_OC0# */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), +/* USB_OC1# */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), +/* USB_OC2# */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), +/* GPIO */ PAD_NC(GPP_E12, NONE), +/* n/a */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), +/* n/a */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), +/* GPIO */ PAD_CFG_GPI_SCI(GPP_E15, NONE, PLTRST, LEVEL, INVERT), +/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_E16, NONE, PLTRST, OFF, ACPI), +/* n/a */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), +/* n/a */ PAD_CFG_NF(GPP_E18, 20K_PU, DEEP, NF1), +/* n/a */ PAD_CFG_NF(GPP_E19, 20K_PD, DEEP, NF1), +/* n/a */ PAD_CFG_NF(GPP_E20, 20K_PU, DEEP, NF1), +/* n/a */ PAD_CFG_NF(GPP_E21, 20K_PD, DEEP, NF1), +/* GPIO */ PAD_CFG_GPIO_BIDIRECT(GPP_E22, 0, NONE, DEEP, OFF, ACPI), +/* GPIO */ PAD_CFG_TERM_GPO(GPP_E23, 1, 20K_PD, DEEP), +/* BATLOW# */ PAD_CFG_NF(GPD0, 20K_PU, PWROK, NF1), +/* ACPRESENT */ PAD_CFG_NF(GPD1, NONE, PWROK, NF1), +/* LAN_WAKE# */ PAD_CFG_NF(GPD2, NATIVE, PWROK, NF1), +/* PWRBTN# */ PAD_CFG_NF(GPD3, 20K_PU, PWROK, NF1), +/* SLP_S3# */ PAD_CFG_NF(GPD4, NONE, PWROK, NF1), +/* SLP_S4# */ PAD_CFG_NF(GPD5, NONE, PWROK, NF1), +/* SLP_A# */ PAD_CFG_NF(GPD6, NONE, PWROK, NF1), +/* GPIO */ PAD_NC(GPD7, NONE), +/* SUSCLK */ PAD_CFG_NF(GPD8, NONE, PWROK, NF1), +/* SLP_WLAN# */ PAD_CFG_NF(GPD9, NONE, PWROK, NF1), +/* SLP_S5# */ PAD_CFG_NF(GPD10, NONE, PWROK, NF1), +/* LANPHYPC */ PAD_CFG_NF(GPD11, NONE, PWROK, NF1), +/* SATAXPCIE3 */ PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), +/* SATAXPCIE4 */ PAD_CFG_NF(GPP_F1, NONE, DEEP, NF1), +/* SATAXPCIE5 */ PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), +/* SATAXPCIE6 */ PAD_CFG_NF(GPP_F3, NONE, DEEP, NF1), +/* SATAXPCIE7 */ PAD_CFG_NF_1V8(GPP_F4, 20K_PU, DEEP, NF1), +/* SATA_DEVSLP3 */ PAD_CFG_NF_1V8(GPP_F5, 20K_PU, DEEP, NF1), +/* SATA_DEVSLP4 */ PAD_CFG_NF_1V8(GPP_F6, 20K_PU, DEEP, NF1), +/* SATA_DEVSLP5 */ PAD_CFG_NF_1V8(GPP_F7, 20K_PU, DEEP, NF1), +/* SATA_DEVSLP6 */ PAD_CFG_NF_1V8(GPP_F8, 20K_PU, DEEP, NF1), +/* SATA_DEVSLP7 */ PAD_CFG_NF_1V8(GPP_F9, 20K_PU, DEEP, NF1), +/* n/a */ PAD_CFG_NF_1V8(GPP_F10, 20K_PU, DEEP, NF2), +/* n/a */ PAD_CFG_NF_1V8(GPP_F11, 20K_PU, DEEP, NF2), +/* SATA_SDATAOUT1 */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), +/* SATA_SDATAOUT2 */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), +/* n/a */ PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), +/* USB_OC4# */ PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), +/* USB_OC5# */ PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), +/* USB_OC6# */ PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1), +/* USB_OC7# */ PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1), +/* eDP_VDDEN */ PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), +/* eDP_BKLTEN */ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), +/* eDP_BKLTCTL */ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), +/* n/a */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), +/* GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_F23, NONE, DEEP, OFF, ACPI), +/* FAN_TACH_0 */ PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1), +/* FAN_TACH_1 */ PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1), +/* FAN_TACH_2 */ PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1), +/* FAN_TACH_3 */ PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1), +/* FAN_TACH_4 */ PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1), +/* FAN_TACH_5 */ PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1), +/* FAN_TACH_6 */ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1), +/* FAN_TACH_7 */ PAD_CFG_NF(GPP_G7, 20K_PD, DEEP, NF1), };
#endif
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Angel Pons (Code Review) -
Matt DeVillier (Code Review)
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Maxim Polyakov (Code Review)
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Michael Niewöhner (Code Review)
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Patrick Georgi (Code Review)