Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52781 )
Change subject: cpu/amd/agesa/family14/model_14_init.c: create correct MTRR solution ......................................................................
cpu/amd/agesa/family14/model_14_init.c: create correct MTRR solution
Create the correct MTRR solution based on the physical address space provided by RESOURCE_ALLOCATOR_V4. Previously CPU initialization did not account for lost C6 DRAM storage MTRR during postcar frame creation. The BSP on 2GB has been stripped from UC MTRR covering C6 DRAM and overlapping with usable DRAM WB MTRR. However this UC MTRR remained on APs which caused inconsistent MTRRs warning in Linux. Use generic MTRR function to create correct MTRR solution that propagates to APs. This also fixes the inconsistent MTRRs warning.
TEST=boot Debian with Linux 4.14 on apu1 2GB
Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com Change-Id: If706f8851ed0b1d45729e81175d82abb1d9193be --- M src/cpu/amd/agesa/family14/model_14_init.c 1 file changed, 30 insertions(+), 42 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/52781/1
diff --git a/src/cpu/amd/agesa/family14/model_14_init.c b/src/cpu/amd/agesa/family14/model_14_init.c index 942539c..f027964 100644 --- a/src/cpu/amd/agesa/family14/model_14_init.c +++ b/src/cpu/amd/agesa/family14/model_14_init.c @@ -12,48 +12,34 @@ #include <cpu/x86/cache.h> #include <acpi/acpi.h> #include <northbridge/amd/agesa/agesa_helper.h> +#include <smp/node.h>
static void model_14_init(struct device *dev) { u8 i; msr_t msr; int num_banks; - int msrno; -#if CONFIG(LOGICAL_CPUS) u32 siblings; -#endif printk(BIOS_DEBUG, "Model 14 Init.\n");
- disable_cache(); - /* - * AGESA sets the MTRRs main MTRRs. The shadow area needs to be set - * by coreboot. The amd_setup_mtrrs should work, but needs debug on fam14. - * TODO: - * amd_setup_mtrrs(); - */
- /* Enable access to AMD RdDram and WrDram extension bits */ - msr = rdmsr(SYSCFG_MSR); - msr.lo |= SYSCFG_MSR_MtrrFixDramModEn; - msr.lo &= ~SYSCFG_MSR_MtrrFixDramEn; - wrmsr(SYSCFG_MSR, msr); - - /* Set shadow WB, RdMEM, WrMEM */ - msr.lo = msr.hi = 0; - wrmsr(MTRR_FIX_16K_A0000, msr); - msr.lo = msr.hi = 0x1e1e1e1e; - wrmsr(MTRR_FIX_64K_00000, msr); - wrmsr(MTRR_FIX_16K_80000, msr); - for (msrno = MTRR_FIX_4K_C0000; msrno <= MTRR_FIX_4K_F8000; msrno++) - wrmsr(msrno, msr); - - msr = rdmsr(SYSCFG_MSR); - msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn; - msr.lo |= SYSCFG_MSR_MtrrFixDramEn; - wrmsr(SYSCFG_MSR, msr); - - if (acpi_is_wakeup_s3()) + if (acpi_is_wakeup_s3()) { restore_mtrr(); + } else { + /* + * All cores are initialized sequentially, so the solution for APs will be + * created before they start. + */ + x86_setup_mtrrs_with_detect(); + /* + * Enable ROM caching on BSP we just lost when creating MTRR solution, for + * faster execution + */ + if (boot_cpu()) { + mtrr_use_temp_range(OPTIMAL_CACHE_ROM_BASE, OPTIMAL_CACHE_ROM_SIZE, + MTRR_TYPE_WRPROT); + } + }
x86_mtrr_check(); x86_enable_cache(); @@ -69,20 +55,20 @@ /* Enable the local CPU APICs */ setup_lapic();
-#if CONFIG(LOGICAL_CPUS) - siblings = cpuid_ecx(0x80000008) & 0xff; + if (CONFIG(LOGICAL_CPUS)) { + siblings = cpuid_ecx(0x80000008) & 0xff;
- if (siblings > 0) { - msr = rdmsr_amd(CPU_ID_FEATURES_MSR); - msr.lo |= 1 << 28; - wrmsr_amd(CPU_ID_FEATURES_MSR, msr); + if (siblings > 0) { + msr = rdmsr_amd(CPU_ID_FEATURES_MSR); + msr.lo |= 1 << 28; + wrmsr_amd(CPU_ID_FEATURES_MSR, msr);
- msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR); - msr.hi |= 1 << (33 - 32); - wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr); + msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR); + msr.hi |= 1 << (33 - 32); + wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr); + } + printk(BIOS_DEBUG, "siblings = %02d, ", siblings); } - printk(BIOS_DEBUG, "siblings = %02d, ", siblings); -#endif
/* DisableCf8ExtCfg */ msr = rdmsr(NB_CFG_MSR); @@ -93,6 +79,8 @@ msr = rdmsr(HWCR_MSR); msr.lo |= (1 << 0); wrmsr(HWCR_MSR, msr); + + display_mtrrs(); }
static struct device_operations cpu_dev_ops = {