Change in coreboot[master]: amdfam10h-15h: Add common romstage entry

[Michał Żygowski (Code Review)]

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62084 )

Change subject: amdfam10h-15h: Add common romstage entry
......................................................................

amdfam10h-15h: Add common romstage entry

Signed-off-by: Michał Żygowski 
Change-Id: I662795a20d69c547fdcb2040887c0f242a37e5b2
---
M src/cpu/amd/family_10h-family_15h/Makefile.inc
A src/cpu/amd/family_10h-family_15h/romstage.c
M src/northbridge/amd/amdfam10/Makefile.inc
A src/northbridge/amd/amdfam10/romstage.c
4 files changed, 82 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/62084/1

diff --git a/src/cpu/amd/family_10h-family_15h/Makefile.inc b/src/cpu/amd/family_10h-family_15h/Makefile.inc
index 64d43eb..8088cc4 100644
--- a/src/cpu/amd/family_10h-family_15h/Makefile.inc
+++ b/src/cpu/amd/family_10h-family_15h/Makefile.inc
@@ -1,6 +1,8 @@
 bootblock-y += bootblock.c
 bootblock-y += cache_as_ram.S

+romstage-y += romstage.c
+
 ifeq ($(CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS),y)
 # Microcode for Family 10h, 11h, 12h, and 14h
 cpu_microcode_bins += 3rdparty/blobs/cpu/amd/family_10h-family_14h/microcode_amd.bin
diff --git a/src/cpu/amd/family_10h-family_15h/romstage.c b/src/cpu/amd/family_10h-family_15h/romstage.c
new file mode 100644
index 0000000..108d0b3
--- /dev/null
+++ b/src/cpu/amd/family_10h-family_15h/romstage.c
@@ -0,0 +1,72 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <arch/cpu.h>
+#include <arch/romstage.h>
+#include <console/console.h>
+#include <cpu/x86/smm.h>
+#include <arch/symbols.h>
+#include <commonlib/helpers.h>
+#include <program_loading.h>
+#include <timestamp.h>
+#include <cbmem.h>
+
+/* If we do not have a constrained _car_stack region size, use the
+   following as a guideline for acceptable stack usage. */
+#define DCACHE_RAM_ROMSTAGE_STACK_SIZE 0x2000
+
+static struct postcar_frame early_mtrrs;
+
+static void romstage_main(void)
+{
+	int i;
+	const int num_guards = 64;
+	const u32 stack_guard = 0xdeadbeef;
+	u32 *stack_base;
+	u32 size;
+	const size_t stack_size = MAX(CONFIG_DCACHE_BSP_STACK_SIZE,
+				      DCACHE_RAM_ROMSTAGE_STACK_SIZE);
+
+	/* Size of unallocated CAR. */
+	size = ALIGN_DOWN(_car_stack_size, 16);
+
+	size = MIN(size, stack_size);
+	if (size < stack_size)
+		printk(BIOS_DEBUG, "Romstage stack size limited to 0x%x!\n",
+			size);
+
+	stack_base = (u32 *) (_ecar_stack - size);
+
+	for (i = 0; i < num_guards; i++)
+		stack_base[i] = stack_guard;
+
+	mainboard_romstage_entry();
+
+	/* Check the stack. */
+	for (i = 0; i < num_guards; i++) {
+		if (stack_base[i] == stack_guard)
+			continue;
+		printk(BIOS_DEBUG, "Smashed stack detected in romstage!\n");
+	}
+
+	prepare_and_run_postcar(&early_mtrrs);
+	/* We do not return here. */
+}
+
+void *cbmem_top_chipset(void)
+{
+	return NULL;
+}
+
+void fill_postcar_frame(struct postcar_frame *pcf)
+{
+}
+
+asmlinkage void car_stage_entry(void)
+{
+	timestamp_add_now(TS_START_ROMSTAGE);
+
+	/* Assumes the hardware was set up during the bootblock */
+	console_init();
+
+	romstage_main();
+}
diff --git a/src/northbridge/amd/amdfam10/Makefile.inc b/src/northbridge/amd/amdfam10/Makefile.inc
index 6c14765..7ccfd66 100644
--- a/src/northbridge/amd/amdfam10/Makefile.inc
+++ b/src/northbridge/amd/amdfam10/Makefile.inc
@@ -1,6 +1,7 @@
 ifeq ($(CONFIG_NORTHBRIDGE_AMD_AMDFAM10),y)

romstage-y += early_ht.c
+romstage-y += romstage.c

ramstage-y += northbridge.c

diff --git a/src/northbridge/amd/amdfam10/romstage.c b/src/northbridge/amd/amdfam10/romstage.c
new file mode 100644
index 0000000..e696021
--- /dev/null
+++ b/src/northbridge/amd/amdfam10/romstage.c
@@ -0,0 +1,7 @@
+#include <arch/romstage.h>
+#include <halt.h>
+
+void mainboard_romstage_entry(void)
+{
+	halt();
+}