Ronak Kanabar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39280 )
Change subject: soc/tigerlake: Correct FSP log interface for JSL ......................................................................
soc/tigerlake: Correct FSP log interface for JSL
Set DEBUG_INTERFACE_TRACEHUB as default and select correct UART. DEBUG_INTERFACE_UART: Legacy UART DEBUG_INTERFACE_SERIAL_IO: PCH UART
BUG=None TEST=boot jslrvp board with Debug FSP and check FSP uart log Signed-off-by: Ronak Kanabar ronak.kanabar@intel.com
Change-Id: I7be7f93082f9c64c1c45963d70ee2e3b3d29986a --- M src/soc/intel/tigerlake/romstage/fsp_params_jsl.c 1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/39280/1
diff --git a/src/soc/intel/tigerlake/romstage/fsp_params_jsl.c b/src/soc/intel/tigerlake/romstage/fsp_params_jsl.c index 56124f4..3dc87ee 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params_jsl.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params_jsl.c @@ -70,7 +70,7 @@ /* Set CPU Ratio */ m_cfg->CpuRatio = 0; m_cfg->PcdDebugInterfaceFlags = CONFIG(DRIVERS_UART_8250IO) ? - DEBUG_INTERFACE_UART : DEBUG_INTERFACE_TRACEHUB; + DEBUG_INTERFACE_UART : DEBUG_INTERFACE_SERIAL_IO;
/* Change VmxEnable UPD value according to ENABLE_VMX Kconfig */ m_cfg->VmxEnable = CONFIG(ENABLE_VMX);
Hello Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39280
to look at the new patch set (#2).
Change subject: soc/intel/tigerlake: Correct FSP log interface for JSL ......................................................................
soc/intel/tigerlake: Correct FSP log interface for JSL
Set DEBUG_INTERFACE_TRACEHUB as default and select correct UART. DEBUG_INTERFACE_UART: Legacy UART DEBUG_INTERFACE_SERIAL_IO: PCH UART
BUG=None TEST=boot jslrvp board with Debug FSP and check FSP uart log Signed-off-by: Ronak Kanabar ronak.kanabar@intel.com
Change-Id: I7be7f93082f9c64c1c45963d70ee2e3b3d29986a --- M src/soc/intel/tigerlake/romstage/fsp_params_jsl.c 1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/39280/2
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39280 )
Change subject: soc/intel/tigerlake: Correct FSP log interface for JSL ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39280/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/39280/2//COMMIT_MSG@9 PS2, Line 9: Set DEBUG_INTERFACE_TRACEHUB as default and select correct UART. Isn't this change actually getting rid of DEBUG_INTERFACE_TRACEHUB setting?
Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Maulik V Vaghela, Rizwan Qureshi, Subrata Banik, Meera Ravindranath, Aamir Bohra, Patrick Rudolph, Karthik Ramasubramanian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39280
to look at the new patch set (#3).
Change subject: soc/intel/tigerlake: Correct FSP log interface for JSL ......................................................................
soc/intel/tigerlake: Correct FSP log interface for JSL
select correct UART settings according to Kconfig DEBUG_INTERFACE_UART: Legacy UART DEBUG_INTERFACE_SERIAL_IO: PCH UART
add check for DEBUG_INTERFACE_TRACEHUB selection.
BUG=None TEST=boot jslrvp board with Debug FSP and check FSP uart log Signed-off-by: Ronak Kanabar ronak.kanabar@intel.com
Change-Id: I7be7f93082f9c64c1c45963d70ee2e3b3d29986a --- M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/romstage/fsp_params_jsl.c 2 files changed, 18 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/39280/3
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39280 )
Change subject: soc/intel/tigerlake: Correct FSP log interface for JSL ......................................................................
Patch Set 3:
(3 comments)
https://review.coreboot.org/c/coreboot/+/39280/3/src/soc/intel/tigerlake/chi... File src/soc/intel/tigerlake/chip.h:
https://review.coreboot.org/c/coreboot/+/39280/3/src/soc/intel/tigerlake/chi... PS3, Line 197: *Select 'Host Debugger' if Trace Hub is used with host debugger tool or 'Target Debugger' line over 96 characters
https://review.coreboot.org/c/coreboot/+/39280/3/src/soc/intel/tigerlake/rom... File src/soc/intel/tigerlake/romstage/fsp_params_jsl.c:
https://review.coreboot.org/c/coreboot/+/39280/3/src/soc/intel/tigerlake/rom... PS3, Line 73: /* UART configration */ 'configration' may be misspelled - perhaps 'configuration'?
https://review.coreboot.org/c/coreboot/+/39280/3/src/soc/intel/tigerlake/rom... PS3, Line 77: /* TraceHub configration */ 'configration' may be misspelled - perhaps 'configuration'?
Ronak Kanabar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39280 )
Change subject: soc/intel/tigerlake: Correct FSP log interface for JSL ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39280/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/39280/2//COMMIT_MSG@9 PS2, Line 9: Set DEBUG_INTERFACE_TRACEHUB as default and select correct UART.
Isn't this change actually getting rid of DEBUG_INTERFACE_TRACEHUB setting?
Ack
Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Maulik V Vaghela, Rizwan Qureshi, Subrata Banik, Meera Ravindranath, Aamir Bohra, Patrick Rudolph, Karthik Ramasubramanian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39280
to look at the new patch set (#4).
Change subject: soc/intel/tigerlake: Correct FSP log interface for JSL ......................................................................
soc/intel/tigerlake: Correct FSP log interface for JSL
select correct UART settings according to Kconfig DEBUG_INTERFACE_UART: Legacy UART DEBUG_INTERFACE_SERIAL_IO: PCH UART
add check for DEBUG_INTERFACE_TRACEHUB selection.
BUG=None TEST=boot jslrvp board with Debug FSP and check FSP uart log Signed-off-by: Ronak Kanabar ronak.kanabar@intel.com
Change-Id: I7be7f93082f9c64c1c45963d70ee2e3b3d29986a --- M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/romstage/fsp_params_jsl.c 2 files changed, 19 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/39280/4
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39280 )
Change subject: soc/intel/tigerlake: Correct FSP log interface for JSL ......................................................................
Patch Set 4:
(2 comments)
https://review.coreboot.org/c/coreboot/+/39280/4/src/soc/intel/tigerlake/chi... File src/soc/intel/tigerlake/chip.h:
https://review.coreboot.org/c/coreboot/+/39280/4/src/soc/intel/tigerlake/chi... PS4, Line 197: *Select 'Host Debugger' if Trace Hub is used with host debugger tool trailing whitespace
https://review.coreboot.org/c/coreboot/+/39280/4/src/soc/intel/tigerlake/chi... PS4, Line 198: *or 'Target Debugger' if Trace Hub is used by target debugger software trailing whitespace
Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Maulik V Vaghela, Rizwan Qureshi, Subrata Banik, Meera Ravindranath, Aamir Bohra, Patrick Rudolph, Karthik Ramasubramanian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39280
to look at the new patch set (#5).
Change subject: soc/intel/tigerlake: Correct FSP log interface for JSL ......................................................................
soc/intel/tigerlake: Correct FSP log interface for JSL
select correct UART settings according to Kconfig DEBUG_INTERFACE_UART: Legacy UART DEBUG_INTERFACE_SERIAL_IO: PCH UART
add check for DEBUG_INTERFACE_TRACEHUB selection.
BUG=None TEST=boot jslrvp board with Debug FSP and check FSP uart log Signed-off-by: Ronak Kanabar ronak.kanabar@intel.com
Change-Id: I7be7f93082f9c64c1c45963d70ee2e3b3d29986a --- M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/romstage/fsp_params_jsl.c 2 files changed, 19 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/39280/5
Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Maulik V Vaghela, Rizwan Qureshi, Subrata Banik, Meera Ravindranath, Aamir Bohra, Patrick Rudolph, Karthik Ramasubramanian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39280
to look at the new patch set (#6).
Change subject: soc/intel/tigerlake: Correct FSP log interface for JSL ......................................................................
soc/intel/tigerlake: Correct FSP log interface for JSL
select correct UART settings according to Kconfig DEBUG_INTERFACE_UART: Legacy UART DEBUG_INTERFACE_SERIAL_IO: PCH UART
add check for DEBUG_INTERFACE_TRACEHUB selection.
BUG=None TEST=boot jslrvp board with Debug FSP and check FSP uart log Signed-off-by: Ronak Kanabar ronak.kanabar@intel.com
Change-Id: I7be7f93082f9c64c1c45963d70ee2e3b3d29986a --- M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/romstage/fsp_params_jsl.c 2 files changed, 19 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/39280/6
Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39280 )
Change subject: soc/intel/tigerlake: Correct FSP log interface for JSL ......................................................................
Patch Set 6:
(3 comments)
https://review.coreboot.org/c/coreboot/+/39280/5//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/39280/5//COMMIT_MSG@13 PS5, Line 13: ACE_TRACEHUB selection and set debuginterface flag accordingly.
https://review.coreboot.org/c/coreboot/+/39280/5/src/soc/intel/tigerlake/chi... File src/soc/intel/tigerlake/chip.h:
https://review.coreboot.org/c/coreboot/+/39280/5/src/soc/intel/tigerlake/chi... PS5, Line 200: Disable, 1: Target Debugger Mode, 2: Host Debugger Mode I think the description in last line says it all, can skip the above lines.
https://review.coreboot.org/c/coreboot/+/39280/5/src/soc/intel/tigerlake/chi... PS5, Line 197: *Select 'Host Debugger' if Trace Hub is used with host debugger tool : *or 'Target Debugger' if Trace Hub is used by target debugger software : *or 'Disable' trace hub functionality. : *0: space after *
Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Maulik V Vaghela, Rizwan Qureshi, Subrata Banik, Meera Ravindranath, Aamir Bohra, Patrick Rudolph, Karthik Ramasubramanian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39280
to look at the new patch set (#7).
Change subject: soc/intel/tigerlake: Correct FSP log interface for JSL ......................................................................
soc/intel/tigerlake: Correct FSP log interface for JSL
select correct UART settings according to Kconfig DEBUG_INTERFACE_UART: Legacy UART DEBUG_INTERFACE_SERIAL_IO: PCH UART
add check for DEBUG_INTERFACE_TRACEHUB selection and set debuginterface flag accordingly.
BUG=None TEST=boot jslrvp board with Debug FSP and check FSP uart log Signed-off-by: Ronak Kanabar ronak.kanabar@intel.com
Change-Id: I7be7f93082f9c64c1c45963d70ee2e3b3d29986a --- M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/romstage/fsp_params_jsl.c 2 files changed, 16 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/39280/7
Ronak Kanabar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39280 )
Change subject: soc/intel/tigerlake: Correct FSP log interface for JSL ......................................................................
Patch Set 7:
(3 comments)
https://review.coreboot.org/c/coreboot/+/39280/5//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/39280/5//COMMIT_MSG@13 PS5, Line 13: ACE_TRACEHUB selection
and set debuginterface flag accordingly.
Ack
https://review.coreboot.org/c/coreboot/+/39280/5/src/soc/intel/tigerlake/chi... File src/soc/intel/tigerlake/chip.h:
https://review.coreboot.org/c/coreboot/+/39280/5/src/soc/intel/tigerlake/chi... PS5, Line 197: *Select 'Host Debugger' if Trace Hub is used with host debugger tool : *or 'Target Debugger' if Trace Hub is used by target debugger software : *or 'Disable' trace hub functionality. : *0:
space after *
Ack
https://review.coreboot.org/c/coreboot/+/39280/5/src/soc/intel/tigerlake/chi... PS5, Line 200: Disable, 1: Target Debugger Mode, 2: Host Debugger Mode
I think the description in last line says it all, can skip the above lines.
Ack
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39280 )
Change subject: soc/intel/tigerlake: Correct FSP log interface for JSL ......................................................................
Patch Set 7:
(3 comments)
I think TGL code needs a similar change as well.
https://review.coreboot.org/c/coreboot/+/39280/7/src/soc/intel/tigerlake/chi... File src/soc/intel/tigerlake/chip.h:
https://review.coreboot.org/c/coreboot/+/39280/7/src/soc/intel/tigerlake/chi... PS7, Line 196: /* TraceHubMode config nit: Use consistent multi-line comment format: /* * TraceHubMode ...
https://review.coreboot.org/c/coreboot/+/39280/7/src/soc/intel/tigerlake/rom... File src/soc/intel/tigerlake/romstage/fsp_params_jsl.c:
https://review.coreboot.org/c/coreboot/+/39280/7/src/soc/intel/tigerlake/rom... PS7, Line 78: nit: blank line not required.
https://review.coreboot.org/c/coreboot/+/39280/7/src/soc/intel/tigerlake/rom... PS7, Line 79: config->TraceHubMode != 0 Don't you also need to ensure that the corresponding device in device tree is enabled?
Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Maulik V Vaghela, Rizwan Qureshi, Subrata Banik, Meera Ravindranath, Aamir Bohra, Patrick Rudolph, Karthik Ramasubramanian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39280
to look at the new patch set (#8).
Change subject: soc/intel/tigerlake: Correct FSP log interface for JSL ......................................................................
soc/intel/tigerlake: Correct FSP log interface for JSL
select correct UART settings according to Kconfig DEBUG_INTERFACE_UART: Legacy UART DEBUG_INTERFACE_SERIAL_IO: PCH UART
add check for DEBUG_INTERFACE_TRACEHUB selection and set debuginterface flag accordingly.
BUG=None TEST=boot jslrvp board with Debug FSP and check FSP uart log Signed-off-by: Ronak Kanabar ronak.kanabar@intel.com
Change-Id: I7be7f93082f9c64c1c45963d70ee2e3b3d29986a --- M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/romstage/fsp_params_jsl.c 2 files changed, 16 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/39280/8
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39280 )
Change subject: soc/intel/tigerlake: Correct FSP log interface for JSL ......................................................................
Patch Set 8:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39280/8/src/soc/intel/tigerlake/chi... File src/soc/intel/tigerlake/chip.h:
https://review.coreboot.org/c/coreboot/+/39280/8/src/soc/intel/tigerlake/chi... PS8, Line 196: /* trailing whitespace
Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Maulik V Vaghela, Rizwan Qureshi, Subrata Banik, Meera Ravindranath, Aamir Bohra, Patrick Rudolph, Karthik Ramasubramanian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39280
to look at the new patch set (#9).
Change subject: soc/intel/tigerlake: Correct FSP log interface for JSL ......................................................................
soc/intel/tigerlake: Correct FSP log interface for JSL
select correct UART settings according to Kconfig DEBUG_INTERFACE_UART: Legacy UART DEBUG_INTERFACE_SERIAL_IO: PCH UART
add check for DEBUG_INTERFACE_TRACEHUB selection and set debuginterface flag accordingly.
BUG=None TEST=boot jslrvp board with Debug FSP and check FSP uart log Signed-off-by: Ronak Kanabar ronak.kanabar@intel.com
Change-Id: I7be7f93082f9c64c1c45963d70ee2e3b3d29986a --- M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/romstage/fsp_params_jsl.c 2 files changed, 16 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/39280/9
Ronak Kanabar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39280 )
Change subject: soc/intel/tigerlake: Correct FSP log interface for JSL ......................................................................
Patch Set 9:
(4 comments)
https://review.coreboot.org/c/coreboot/+/39280/8/src/soc/intel/tigerlake/chi... File src/soc/intel/tigerlake/chip.h:
https://review.coreboot.org/c/coreboot/+/39280/8/src/soc/intel/tigerlake/chi... PS8, Line 196: /*
trailing whitespace
Done
https://review.coreboot.org/c/coreboot/+/39280/7/src/soc/intel/tigerlake/chi... File src/soc/intel/tigerlake/chip.h:
https://review.coreboot.org/c/coreboot/+/39280/7/src/soc/intel/tigerlake/chi... PS7, Line 196: /* TraceHubMode config
nit: Use consistent multi-line comment format: […]
Done
https://review.coreboot.org/c/coreboot/+/39280/7/src/soc/intel/tigerlake/rom... File src/soc/intel/tigerlake/romstage/fsp_params_jsl.c:
https://review.coreboot.org/c/coreboot/+/39280/7/src/soc/intel/tigerlake/rom... PS7, Line 78:
nit: blank line not required.
Done
https://review.coreboot.org/c/coreboot/+/39280/7/src/soc/intel/tigerlake/rom... PS7, Line 79: config->TraceHubMode != 0
Don't you also need to ensure that the corresponding device in device tree is enabled?
Done
Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Maulik V Vaghela, Rizwan Qureshi, Subrata Banik, Meera Ravindranath, Aamir Bohra, Patrick Rudolph, Karthik Ramasubramanian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39280
to look at the new patch set (#10).
Change subject: soc/intel/tigerlake: Correct FSP log interface ......................................................................
soc/intel/tigerlake: Correct FSP log interface
select correct UART settings according to Kconfig DEBUG_INTERFACE_UART: Legacy UART DEBUG_INTERFACE_SERIAL_IO: PCH UART
add check for DEBUG_INTERFACE_TRACEHUB selection and set debuginterface flag accordingly.
BUG=None TEST=boot jslrvp/tglrvp board with Debug FSP and check FSP uart log Signed-off-by: Ronak Kanabar ronak.kanabar@intel.com
Change-Id: I7be7f93082f9c64c1c45963d70ee2e3b3d29986a --- M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/romstage/fsp_params_jsl.c M src/soc/intel/tigerlake/romstage/fsp_params_tgl.c 3 files changed, 27 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/39280/10
Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Maulik V Vaghela, Rizwan Qureshi, Subrata Banik, Meera Ravindranath, Aamir Bohra, Patrick Rudolph, Karthik Ramasubramanian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39280
to look at the new patch set (#11).
Change subject: soc/intel/tigerlake: Correct FSP log interface ......................................................................
soc/intel/tigerlake: Correct FSP log interface
select correct UART settings according to Kconfig DEBUG_INTERFACE_UART: Legacy UART DEBUG_INTERFACE_SERIAL_IO: PCH UART
add check for DEBUG_INTERFACE_TRACEHUB selection and set debuginterface flag accordingly.
BUG=None TEST=boot jslrvp/tglrvp board with Debug FSP and check FSP uart log Signed-off-by: Ronak Kanabar ronak.kanabar@intel.com
Change-Id: I7be7f93082f9c64c1c45963d70ee2e3b3d29986a --- M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/romstage/fsp_params_jsl.c 2 files changed, 16 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/39280/11
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39280 )
Change subject: soc/intel/tigerlake: Correct FSP log interface ......................................................................
Patch Set 11: Code-Review+1
(2 comments)
https://review.coreboot.org/c/coreboot/+/39280/11//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/39280/11//COMMIT_MSG@14 PS11, Line 14: debuginterface missing a space?
https://review.coreboot.org/c/coreboot/+/39280/11//COMMIT_MSG@17 PS11, Line 17: uart UART
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39280 )
Change subject: soc/intel/tigerlake: Correct FSP log interface ......................................................................
Patch Set 11:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39280/11/src/soc/intel/tigerlake/ro... File src/soc/intel/tigerlake/romstage/fsp_params_jsl.c:
https://review.coreboot.org/c/coreboot/+/39280/11/src/soc/intel/tigerlake/ro... PS11, Line 78: pcidev_path_on_root(PCH_DEVFN_TRACEHUB) What about checking enabled?
Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39280 )
Change subject: soc/intel/tigerlake: Correct FSP log interface ......................................................................
Patch Set 11:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39280/11//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/39280/11//COMMIT_MSG@18 PS11, Line 18: Signed Move Signed-off-by after Change-Id line
Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Maulik V Vaghela, Rizwan Qureshi, Angel Pons, Subrata Banik, Meera Ravindranath, Aamir Bohra, Patrick Rudolph, Karthik Ramasubramanian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39280
to look at the new patch set (#12).
Change subject: soc/intel/tigerlake: Correct FSP log interface ......................................................................
soc/intel/tigerlake: Correct FSP log interface
select correct UART settings according to Kconfig DEBUG_INTERFACE_UART: Legacy UART DEBUG_INTERFACE_SERIAL_IO: PCH UART
add check for DEBUG_INTERFACE_TRACEHUB selection and set debuginterface flag accordingly.
BUG=None TEST=boot jslrvp/tglrvp board with Debug FSP and check FSP uart log Signed-off-by: Ronak Kanabar ronak.kanabar@intel.com
Change-Id: I7be7f93082f9c64c1c45963d70ee2e3b3d29986a --- M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/romstage/fsp_params_jsl.c 2 files changed, 17 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/39280/12
Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Maulik V Vaghela, Rizwan Qureshi, Angel Pons, Subrata Banik, Meera Ravindranath, Aamir Bohra, Patrick Rudolph, Karthik Ramasubramanian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39280
to look at the new patch set (#13).
Change subject: soc/intel/tigerlake: Correct FSP log interface ......................................................................
soc/intel/tigerlake: Correct FSP log interface
select correct UART settings according to Kconfig DEBUG_INTERFACE_UART: Legacy UART DEBUG_INTERFACE_SERIAL_IO: PCH UART
add check for DEBUG_INTERFACE_TRACEHUB selection and set debuginterface flag accordingly.
BUG=None TEST=boot jslrvp board with Debug FSP and check FSP uart log Change-Id: I7be7f93082f9c64c1c45963d70ee2e3b3d29986a Signed-off-by: Ronak Kanabar ronak.kanabar@intel.com --- M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/romstage/fsp_params_jsl.c 2 files changed, 17 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/39280/13
Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Maulik V Vaghela, Rizwan Qureshi, Angel Pons, Subrata Banik, Meera Ravindranath, Aamir Bohra, Patrick Rudolph, Karthik Ramasubramanian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39280
to look at the new patch set (#14).
Change subject: soc/intel/tigerlake: Correct FSP log interface ......................................................................
soc/intel/tigerlake: Correct FSP log interface
select correct UART settings according to Kconfig DEBUG_INTERFACE_UART: Legacy UART DEBUG_INTERFACE_SERIAL_IO: PCH UART
add check for DEBUG_INTERFACE_TRACEHUB selection and set debug interface flag accordingly.
BUG=None TEST=boot jslrvp board with Debug FSP and check FSP UART log Change-Id: I7be7f93082f9c64c1c45963d70ee2e3b3d29986a Signed-off-by: Ronak Kanabar ronak.kanabar@intel.com --- M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/romstage/fsp_params_jsl.c 2 files changed, 17 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/39280/14
Ronak Kanabar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39280 )
Change subject: soc/intel/tigerlake: Correct FSP log interface ......................................................................
Patch Set 14:
(3 comments)
https://review.coreboot.org/c/coreboot/+/39280/11//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/39280/11//COMMIT_MSG@14 PS11, Line 14: debuginterface
missing a space?
Done
https://review.coreboot.org/c/coreboot/+/39280/11//COMMIT_MSG@17 PS11, Line 17: uart
UART
Done
https://review.coreboot.org/c/coreboot/+/39280/11//COMMIT_MSG@18 PS11, Line 18: Signed
Move Signed-off-by after Change-Id line
Done
Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Maulik V Vaghela, Rizwan Qureshi, Angel Pons, Subrata Banik, Meera Ravindranath, Aamir Bohra, Patrick Rudolph, Karthik Ramasubramanian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39280
to look at the new patch set (#15).
Change subject: soc/intel/tigerlake: Correct FSP log interface ......................................................................
soc/intel/tigerlake: Correct FSP log interface
select correct UART settings according to Kconfig DEBUG_INTERFACE_UART: Legacy UART DEBUG_INTERFACE_SERIAL_IO: PCH UART
add check for DEBUG_INTERFACE_TRACEHUB selection and set "PcdDebugInterfaceFlags" UPD accordingly.
BUG=None TEST=boot jslrvp board with Debug FSP and check FSP UART log Change-Id: I7be7f93082f9c64c1c45963d70ee2e3b3d29986a Signed-off-by: Ronak Kanabar ronak.kanabar@intel.com --- M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/romstage/fsp_params_jsl.c 2 files changed, 17 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/39280/15
Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39280 )
Change subject: soc/intel/tigerlake: Correct FSP log interface ......................................................................
Patch Set 15:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39280/15/src/soc/intel/tigerlake/ro... File src/soc/intel/tigerlake/romstage/fsp_params_jsl.c:
https://review.coreboot.org/c/coreboot/+/39280/15/src/soc/intel/tigerlake/ro... PS15, Line 29: const struct device *tracehub = pcidev_path_on_root(PCH_DEVFN_TRACEHUB); you can use the dev variable:
dev = pcidev_path_on_root(PCH_DEVFN_TRACEHUB); if (dev && dev->enabled && config->TraceHubMode) { m_cfg->PcdDebugInterfaceFlags |= DEBUG_INTERFACE_TRACEHUB; m_cfg->PchTraceHubMode = config->TraceHubMode; m_cfg->CpuTraceHubMode = config->TraceHubMode; }
Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Maulik V Vaghela, Rizwan Qureshi, Angel Pons, Subrata Banik, Meera Ravindranath, Aamir Bohra, Patrick Rudolph, Karthik Ramasubramanian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39280
to look at the new patch set (#16).
Change subject: soc/intel/tigerlake: Correct FSP log interface ......................................................................
soc/intel/tigerlake: Correct FSP log interface
select correct UART settings according to Kconfig DEBUG_INTERFACE_UART: Legacy UART DEBUG_INTERFACE_SERIAL_IO: PCH UART
add check for DEBUG_INTERFACE_TRACEHUB selection and set "PcdDebugInterfaceFlags" UPD accordingly.
BUG=None TEST=boot jslrvp board with Debug FSP and check FSP UART log Change-Id: I7be7f93082f9c64c1c45963d70ee2e3b3d29986a Signed-off-by: Ronak Kanabar ronak.kanabar@intel.com --- M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/romstage/fsp_params_jsl.c 2 files changed, 17 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/39280/16
Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Maulik V Vaghela, Rizwan Qureshi, Angel Pons, Subrata Banik, Meera Ravindranath, Aamir Bohra, Patrick Rudolph, Karthik Ramasubramanian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39280
to look at the new patch set (#17).
Change subject: soc/intel/tigerlake: Correct FSP log interface ......................................................................
soc/intel/tigerlake: Correct FSP log interface
select correct UART settings according to Kconfig DEBUG_INTERFACE_UART: Legacy UART DEBUG_INTERFACE_SERIAL_IO: PCH UART
add check for DEBUG_INTERFACE_TRACEHUB selection and set "PcdDebugInterfaceFlags" UPD accordingly.
BUG=None TEST=boot jslrvp board with Debug FSP and check FSP UART log Change-Id: I7be7f93082f9c64c1c45963d70ee2e3b3d29986a Signed-off-by: Ronak Kanabar ronak.kanabar@intel.com --- M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/romstage/fsp_params_jsl.c 2 files changed, 17 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/39280/17
Ronak Kanabar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39280 )
Change subject: soc/intel/tigerlake: Correct FSP log interface ......................................................................
Patch Set 17:
(2 comments)
https://review.coreboot.org/c/coreboot/+/39280/11/src/soc/intel/tigerlake/ro... File src/soc/intel/tigerlake/romstage/fsp_params_jsl.c:
https://review.coreboot.org/c/coreboot/+/39280/11/src/soc/intel/tigerlake/ro... PS11, Line 78: pcidev_path_on_root(PCH_DEVFN_TRACEHUB)
What about checking enabled?
Done
https://review.coreboot.org/c/coreboot/+/39280/15/src/soc/intel/tigerlake/ro... File src/soc/intel/tigerlake/romstage/fsp_params_jsl.c:
https://review.coreboot.org/c/coreboot/+/39280/15/src/soc/intel/tigerlake/ro... PS15, Line 29: const struct device *tracehub = pcidev_path_on_root(PCH_DEVFN_TRACEHUB);
you can use the dev variable: […]
Done
Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39280 )
Change subject: soc/intel/tigerlake: Correct FSP log interface ......................................................................
Patch Set 17:
(2 comments)
https://review.coreboot.org/c/coreboot/+/39280/17//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/39280/17//COMMIT_MSG@13 PS17, Line 13: add Add
https://review.coreboot.org/c/coreboot/+/39280/17/src/soc/intel/tigerlake/ro... File src/soc/intel/tigerlake/romstage/fsp_params_jsl.c:
https://review.coreboot.org/c/coreboot/+/39280/17/src/soc/intel/tigerlake/ro... PS17, Line 73: UART configuration not really, I think we are just setting the debug interface flag based on the UART interface.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39280 )
Change subject: soc/intel/tigerlake: Correct FSP log interface ......................................................................
Patch Set 17: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/39280/17/src/soc/intel/tigerlake/ro... File src/soc/intel/tigerlake/romstage/fsp_params_jsl.c:
https://review.coreboot.org/c/coreboot/+/39280/17/src/soc/intel/tigerlake/ro... PS17, Line 73: UART configuration
not really, I think we are just setting the debug interface flag based on the UART interface.
maybe: Set debug interface
Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Maulik V Vaghela, Rizwan Qureshi, Angel Pons, Subrata Banik, Meera Ravindranath, Aamir Bohra, Patrick Rudolph, Karthik Ramasubramanian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39280
to look at the new patch set (#18).
Change subject: soc/intel/tigerlake: Correct FSP log interface ......................................................................
soc/intel/tigerlake: Correct FSP log interface
select correct UART settings according to Kconfig DEBUG_INTERFACE_UART: Legacy UART DEBUG_INTERFACE_SERIAL_IO: PCH UART
Add check for DEBUG_INTERFACE_TRACEHUB selection and set "PcdDebugInterfaceFlags" UPD accordingly.
BUG=None TEST=boot jslrvp board with Debug FSP and check FSP UART log Change-Id: I7be7f93082f9c64c1c45963d70ee2e3b3d29986a Signed-off-by: Ronak Kanabar ronak.kanabar@intel.com --- M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/romstage/fsp_params_jsl.c 2 files changed, 17 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/39280/18
Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Maulik V Vaghela, Rizwan Qureshi, Angel Pons, Subrata Banik, Meera Ravindranath, Aamir Bohra, Patrick Rudolph, Karthik Ramasubramanian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39280
to look at the new patch set (#19).
Change subject: soc/intel/tigerlake: Correct FSP log interface ......................................................................
soc/intel/tigerlake: Correct FSP log interface
select correct UART settings according to Kconfig DEBUG_INTERFACE_UART: Legacy UART DEBUG_INTERFACE_SERIAL_IO: PCH UART
Add check for DEBUG_INTERFACE_TRACEHUB selection and set "PcdDebugInterfaceFlags" UPD accordingly.
BUG=None TEST=boot jslrvp board with Debug FSP and check FSP UART log Change-Id: I7be7f93082f9c64c1c45963d70ee2e3b3d29986a Signed-off-by: Ronak Kanabar ronak.kanabar@intel.com --- M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/romstage/fsp_params_jsl.c 2 files changed, 17 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/39280/19
Ronak Kanabar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39280 )
Change subject: soc/intel/tigerlake: Correct FSP log interface ......................................................................
Patch Set 19:
(2 comments)
https://review.coreboot.org/c/coreboot/+/39280/17//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/39280/17//COMMIT_MSG@13 PS17, Line 13: add
Add
Done
https://review.coreboot.org/c/coreboot/+/39280/17/src/soc/intel/tigerlake/ro... File src/soc/intel/tigerlake/romstage/fsp_params_jsl.c:
https://review.coreboot.org/c/coreboot/+/39280/17/src/soc/intel/tigerlake/ro... PS17, Line 73: UART configuration
maybe: Set debug interface
Done
Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39280 )
Change subject: soc/intel/tigerlake: Correct FSP log interface ......................................................................
Patch Set 19: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/39280 )
Change subject: soc/intel/tigerlake: Correct FSP log interface ......................................................................
soc/intel/tigerlake: Correct FSP log interface
select correct UART settings according to Kconfig DEBUG_INTERFACE_UART: Legacy UART DEBUG_INTERFACE_SERIAL_IO: PCH UART
Add check for DEBUG_INTERFACE_TRACEHUB selection and set "PcdDebugInterfaceFlags" UPD accordingly.
BUG=None TEST=boot jslrvp board with Debug FSP and check FSP UART log Change-Id: I7be7f93082f9c64c1c45963d70ee2e3b3d29986a Signed-off-by: Ronak Kanabar ronak.kanabar@intel.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/39280 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Aamir Bohra aamir.bohra@intel.com --- M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/romstage/fsp_params_jsl.c 2 files changed, 17 insertions(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Aamir Bohra: Looks good to me, approved
diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index d2ea0dd..d23148a 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -193,6 +193,12 @@ */ uint8_t SerialIoGSpiCsState[CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX];
+ /* + * TraceHubMode config + * 0: Disable, 1: Target Debugger Mode, 2: Host Debugger Mode + */ + uint8_t TraceHubMode; + /* Debug interface selection */ enum { DEBUG_INTERFACE_RAM = (1 << 0), diff --git a/src/soc/intel/tigerlake/romstage/fsp_params_jsl.c b/src/soc/intel/tigerlake/romstage/fsp_params_jsl.c index 9c70f2e..a5c4c90 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params_jsl.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params_jsl.c @@ -69,8 +69,18 @@
/* Set CPU Ratio */ m_cfg->CpuRatio = 0; + + /* Set debug interface flags */ m_cfg->PcdDebugInterfaceFlags = CONFIG(DRIVERS_UART_8250IO) ? - DEBUG_INTERFACE_UART : DEBUG_INTERFACE_TRACEHUB; + DEBUG_INTERFACE_UART : DEBUG_INTERFACE_SERIAL_IO; + + /* TraceHub configuration */ + dev = pcidev_path_on_root(PCH_DEVFN_TRACEHUB); + if (dev && dev->enabled && config->TraceHubMode) { + m_cfg->PcdDebugInterfaceFlags |= DEBUG_INTERFACE_TRACEHUB; + m_cfg->PchTraceHubMode = config->TraceHubMode; + m_cfg->CpuTraceHubMode = config->TraceHubMode; + }
/* Change VmxEnable UPD value according to ENABLE_VMX Kconfig */ m_cfg->VmxEnable = CONFIG(ENABLE_VMX);
-
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